/src/tests/lib/libc/gen/ |
t_floatunditf.c | 46 { 0xffffffffffffffffULL, 0xf.fffffffffffffffp+60L }, 47 { 0xfffffffffffffffeULL, 0xf.ffffffffffffffep+60L }, 48 { 0xfffffffffffffffdULL, 0xf.ffffffffffffffdp+60L }, 49 { 0xfffffffffffffffcULL, 0xf.ffffffffffffffcp+60L }, 50 { 0x7fffffffffffffffULL, 0xf.ffffffffffffffep+59L }, 51 { 0x3fffffffffffffffULL, 0xf.ffffffffffffffcp+58L }, 52 { 0x1fffffffffffffffULL, 0xf.ffffffffffffff8p+57L }, 53 { 0xfffffffffffffffULL, 0xf.ffffffffffffffp+56L }, 54 { 0x7ffffffffffffffULL, 0xf.fffffffffffffep+55L }, 55 { 0x3ffffffffffffffULL, 0xf.fffffffffffffcp+54L } [all...] |
/src/sys/arch/sparc/include/ |
cdefs.h | 8 #define __ALIGNBYTES ((size_t)0xf)
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/src/sys/arch/atari/dev/ |
grfabs_tt.h | 38 ((((0x00000f00 & (v)) * 0xff / 0xf) << 8) |\ 39 (((0x000000f0 & (v)) * 0xff / 0xf) << 4) |\ 40 (0x0000000f & (v)) * 0xff / 0xf)
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/src/sys/arch/arm/imx/ |
imxssireg.h | 92 #define WL_MASK (0xf << 13) 94 #define DC_MASK (0xf << 8) 96 #define SFCSR_RFCNT1_MASK (0xf << 28) 97 #define SFCSR_TFCNT1_MASK (0xf << 24) 98 #define SFCSR_RFWM1_MASK (0xf << 20) 99 #define SFCSR_TFWM1_MASK (0xf << 16) 100 #define SFCSR_RFCNT0_MASK (0xf << 12) 101 #define SFCSR_TFCNT0_MASK (0xf << 8) 102 #define SFCSR_RFWM0_MASK (0xf << 4) 103 #define SFCSR_TFWM0_MASK (0xf << 0 [all...] |
/src/usr.sbin/bta2dpd/bta2dpd/ |
sbc_encode.h | 49 #define MODE_ANY 0xf 59 #define FREQ_ANY 0xf 70 #define BLOCKS_ANY 0xf
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/src/sys/arch/i386/stand/pxeboot/ |
pxeboot.h | 39 #define VTOPOFF(vaddr) (vtophys(vaddr) & 0xf)
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/src/sys/dev/eisa/ |
eisareg.h | 91 (HEXDIGITS[(((pid)[0] >> 4) & 0xf)]) 93 (HEXDIGITS[(((pid)[0] >> 0) & 0xf)]) 95 (HEXDIGITS[(((pid)[1] >> 4) & 0xf)]) 97 (HEXDIGITS[(((pid)[1] >> 0) & 0xf)])
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/src/sys/arch/evbmips/alchemy/ |
dbau1500reg.h | 49 #define DBAU1500_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) 50 #define DBAU1500_WHOAMI_DAUGHTER(x) ((x) & 0xf)
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/src/sys/dev/pci/ |
pciide_acard_reg.h | 31 (((((act) & 0xf) << 8) | ((rec) & 0xf)) << ((drive) * 16)) 33 (((((act) & 0xf) << 4) | ((rec) & 0xf)) << \ 50 (((x) & 0xf) << ((channel) * 8 + (drive) * 4)) 51 #define ATP850_UDMA_MASK(channel) (0xf << ((channel) * 4))
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/sound/ |
fsl-imx-audmux.h | 43 #define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) 46 #define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) 52 #define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) 54 #define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) 56 #define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) 58 #define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
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/src/sys/arch/hppa/stand/common/ |
exec_som.c | 47 struct som_filehdr *xf = &xp->xp_hdr->x_som; local in function:som_load 50 if (lseek(fd, xf->aux_loc, SEEK_SET) < 0 || 62 xp->sym.size = xf->sym_total * sizeof(struct som_sym); 63 xp->str.size = xf->strings_size; 68 if (xf->sym_total) { 69 xp->sym.foff = xf->sym_loc; 70 xp->str.foff = xf->strings_loc;
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/src/sys/arch/hpcmips/tx/ |
tx39spireg.h | 47 #define TX39_SPICTRL_DELAYVAL_MASK 0xf 56 #define TX39_SPICTRL_BAUDRATE_MASK 0xf 84 #define TX39_SPICTRL_RXDATA_MASK 0xf
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tx39biureg.h | 151 #define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 159 #define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 177 #define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 187 #define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 197 #define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 207 #define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 240 #define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 250 #define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 260 #define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 270 #define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf [all...] |
tx39sibreg.h | 146 #define TX39_SIBSF0_REGADDR_MASK 0xf 177 #define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf 183 #define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf 189 #define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf 195 #define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf 201 #define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf 214 #define TX39_SIBSF1STAT_ERROR_MASK 0xf 220 #define TX39_SIBSF1STAT_REVISION_MASK 0xf 226 #define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf
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/src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/ |
sanitizer_linux_x86_64.S | 19 mov $0xf, %eax // 0xf == SYS_rt_sigreturn
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/src/sys/arch/mips/alchemy/dev/ |
ausmbus_pscreg.h | 217 #define SMBUS_TMR_STD_PS 0xf 218 #define SMBUS_TMR_STD_PU 0xf 219 #define SMBUS_TMR_STD_SH 0xf 220 #define SMBUS_TMR_STD_SU 0xf 221 #define SMBUS_TMR_STD_CL 0xf 222 #define SMBUS_TMR_STD_CH 0xf 226 #define SMBUS_TMR_FAST_PS 0xf 230 #define SMBUS_TMR_FAST_CL 0xf
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/src/sys/arch/x68k/dev/ |
intio_dmac.c | 277 struct dmac_dma_xfer *xf = &chan->ch_xfer; local in function:dmac_alloc_xfer 280 xf->dx_channel = chan; 281 xf->dx_dmamap = dmamap; 282 xf->dx_tag = dmat; 284 xf->dx_array = chan->ch_map; 285 xf->dx_done = 0; 287 return xf; 291 dmac_load_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf) 293 struct dmac_channel_stat *chan = xf->dx_channel; 297 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK 318 struct dmac_dma_xfer *xf; local in function:dmac_prepare_xfer 480 struct dmac_dma_xfer *xf = &chan->ch_xfer; local in function:dmac_done [all...] |
/src/sys/arch/hpcmips/vr/ |
bcureg.h | 172 #define BCUROMSPEED_ATIME (0xf) /* Access time */ 173 #define BCUROMSPEED_ATIME_18VT (0xf) /* 18VTClock */ 199 #define BCUIO0SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */ 200 #define BCUIO0SPEED_RDYRW_18VT (0xf) /* 18VTClock */ 217 #define BCUIO0SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */ 218 #define BCUIO0SPEED_RWRDY_14VT (0xf) /* 14VTClock */ 235 #define BCUIO0SPEED_CSRW (0xf<<0) /* IORDY-R/W time */ 236 #define BCUIO0SPEED_CSRW_16VT (0xf) /* 16VTClock */ 262 #define BCUIO1SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */ 263 #define BCUIO1SPEED_RDYRW_18VT (0xf) /* 18VTClock * [all...] |
/src/sys/arch/alpha/stand/common/ |
putulong.c | 35 *bp++ = hexdigits[ul & 0xf];
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/src/sys/arch/landisk/stand/boot/ |
prf.c | 49 putchar(hexchar[(val >> (i * 4)) & 0xf]);
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/src/sys/dev/mca/ |
3c523reg.h | 37 #define ELMC_REVISION_MASK 0xf
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/ |
mt65xx.h | 14 #define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
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/src/tests/usr.bin/xlint/lint1/ |
gcc_bit_field_types.c | 43 return lbf.member & 0xf;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
amdgpu_dcn10_mpc.c | 148 if (top_sel == 0xf && opp_id == 0xf && idle) 162 if (top_sel == 0xf) { 225 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 295 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); 314 MPCC_BOT_SEL, 0xf); 323 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 324 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 325 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 329 mpcc_to_remove->dpp_id = 0xf; [all...] |
/src/tests/lib/libc/locale/ |
t_ducet.c | 100 wchar_t *oxf = xfb1, *xf = xfb2; 124 wcsxfrm(xf, line, BUFLEN); 125 result = wcscmp(oxf, xf); 131 for (i = 0; xf[i] != 0; i++) 140 oxf = xf; 141 xf = tmp;
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