| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| H A D | sna_cpu.c | 70 features |= AVX;
112 if (features & AVX)
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| H A D | sna_cpu.c | 70 features |= AVX;
112 if (features & AVX)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/ |
| H A D | simdlib_128_avx2.inl | 28 // SIMD4 AVX (2) implementation
30 // Since this implementation inherits from the AVX (1) implementation,
31 // the only operations below ones that replace AVX (1) operations.
32 // Only 2 shifts and 2 gathers were introduced with AVX 2
|
| H A D | simdlib_256_avx512_core.inl | 28 // SIMD256 AVX (512) implementation for Core processors
30 // Since this implementation inherits from the AVX (2) implementation,
31 // the only operations below ones that replace AVX (2) operations.
|
| H A D | simdlib_128_avx512_core.inl | 28 // SIMD128 AVX (512) implementation
30 // Since this implementation inherits from the AVX (2) implementation,
31 // the only operations below ones that replace AVX (2) operations.
|
| H A D | simdlib_256_avx2.inl | 28 // SIMD256 AVX (2) implementation
30 // Since this implementation inherits from the AVX (1) implementation,
31 // the only operations below ones that replace AVX (1) operations.
|
| H A D | isa.hpp | 106 bool AVX(void) { return CPU_Rep.f_1_ECX_[28]; } function in class:InstructionSet
|
| H A D | simdlib_512_emu.inl | 28 // SIMD16 AVX (1) implementation
576 // Since the 256-bit AVX instructions use a 4-bit control field (instead
578 // AVX instructions for emulation.
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/ |
| H A D | openswr.rst | 10 This rasterizer is x86 specific and requires AVX or above. The driver
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/ |
| H A D | simdlib_128_avx2.inl | 28 // SIMD4 AVX (2) implementation
30 // Since this implementation inherits from the AVX (1) implementation,
31 // the only operations below ones that replace AVX (1) operations.
32 // Only 2 shifts and 2 gathers were introduced with AVX 2
|
| H A D | simdlib_256_avx512_core.inl | 28 // SIMD256 AVX (512) implementation for Core processors
30 // Since this implementation inherits from the AVX (2) implementation,
31 // the only operations below ones that replace AVX (2) operations.
|
| H A D | simdlib_128_avx512_core.inl | 28 // SIMD128 AVX (512) implementation
30 // Since this implementation inherits from the AVX (2) implementation,
31 // the only operations below ones that replace AVX (2) operations.
|
| H A D | simdlib_256_avx2.inl | 28 // SIMD256 AVX (2) implementation
30 // Since this implementation inherits from the AVX (1) implementation,
31 // the only operations below ones that replace AVX (1) operations.
|
| H A D | isa.hpp | 106 bool AVX(void) { return CPU_Rep.f_1_ECX_[28]; } function in class:InstructionSet
|
| H A D | simdlib_512_emu.inl | 28 // SIMD16 AVX (1) implementation
576 // Since the 256-bit AVX instructions use a 4-bit control field (instead
578 // AVX instructions for emulation.
|
| /xsrc/external/mit/MesaLib/dist/docs/drivers/ |
| H A D | openswr.rst | 10 This rasterizer is x86 specific and requires AVX or above. The driver
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/ |
| H A D | knobs.h | 54 #define KNOB_ARCH_ISA AVX
55 #define KNOB_ARCH_STR "AVX"
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/openswr/ |
| H A D | usage.rst | 7 * An x86 processor with AVX or above
|
| H A D | faq.rst | 114 * If using an AMD processor with AVX or AVX2, it should work though
121 * Not without a lot of work. We make extensive use of AVX and AVX2
128 * Any x86 processor with at least AVX (introduced in the Intel
135 Does one build work on both AVX and AVX2?
|
| /xsrc/external/mit/MesaLib/dist/docs/drivers/openswr/ |
| H A D | usage.rst | 7 * An x86 processor with AVX or above
|
| H A D | faq.rst | 114 * If using an AMD processor with AVX or AVX2, it should work though
121 * Not without a lot of work. We make extensive use of AVX and AVX2
128 * Any x86 processor with at least AVX (introduced in the Intel
135 Does one build work on both AVX and AVX2?
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/ |
| H A D | lower_x86.cpp | 49 AVX = 0, enumerator in enum:SwrJit::TargetArch
108 // AVX
203 else if (JM()->mArch.AVX())
205 mTarget = AVX;
209 SWR_ASSERT(false, "Unsupported AVX architecture.");
210 mTarget = AVX;
451 // Only need vperm emulation for AVX
452 SWR_ASSERT(arch == AVX);
492 if (arch == AVX)
494 // Full emulation for AVX
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/ |
| H A D | lower_x86.cpp | 53 AVX = 0, enumerator in enum:SwrJit::TargetArch
123 // AVX
200 else if (JM()->mArch.AVX())
202 mTarget = AVX;
206 SWR_ASSERT(false, "Unsupported AVX architecture.");
207 mTarget = AVX;
500 // Only need vperm emulation for AVX
501 SWR_ASSERT(arch == AVX);
559 if (arch == AVX)
561 // Full emulation for AVX
[all...] |
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 11.0.5.rst | 134 - gallivm: disable f16c when not using AVX
|
| H A D | 17.1.6.rst | 87 - swr: don't forget to link AVX/AVX2 against pthreads
|