Searched refs:Align (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dbuilder_mem.h79 unsigned Align,
86 return IRB()->CreateMaskedLoad(Ptr, Align, Mask, PassThru, Name);
96 virtual CallInst* MASKED_STORE(Value *Val, Value *Ptr, unsigned Align, Value *Mask, Type* Ty = nullptr, JIT_MEM_CLIENT usage = JIT_MEM_CLIENT::MEM_CLIENT_INTERNAL) argument
98 return IRB()->CreateMaskedStore(Val, Ptr, Align, Mask);
78 MASKED_LOAD(Value * Ptr,unsigned Align,Value * Mask,Value * PassThru=nullptr,const Twine & Name="",Type * Ty=nullptr,JIT_MEM_CLIENT usage=JIT_MEM_CLIENT::MEM_CLIENT_INTERNAL) argument
H A Dbuilder_gfx_mem.h72 unsigned Align,
83 virtual CallInst* MASKED_STORE(Value *Val, Value *Ptr, unsigned Align, Value *Mask, Type* Ty = nullptr, JIT_MEM_CLIENT usage = JIT_MEM_CLIENT::MEM_CLIENT_INTERNAL);
H A Dbuilder_gfx_mem.cpp227 unsigned Align,
237 return Builder::MASKED_LOAD(Ptr, Align, Mask, PassThru, Name, Ty, usage);
256 CallInst* BuilderGfxMem::MASKED_STORE(Value *Val, Value *Ptr, unsigned Align, Value *Mask, Type* Ty, JIT_MEM_CLIENT usage) argument
261 return Builder::MASKED_STORE(Val, Ptr, Align, Mask, Ty, usage);
226 MASKED_LOAD(Value * Ptr,unsigned Align,Value * Mask,Value * PassThru,const Twine & Name,Type * Ty,JIT_MEM_CLIENT usage) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dbuilder_mem.h80 unsigned Align,
87 return IRB()->CreateMaskedLoad(Ptr, AlignType(Align), Mask, PassThru, Name);
97 virtual CallInst* MASKED_STORE(Value *Val, Value *Ptr, unsigned Align, Value *Mask, Type* Ty = nullptr, MEM_CLIENT usage = MEM_CLIENT::MEM_CLIENT_INTERNAL) argument
99 return IRB()->CreateMaskedStore(Val, Ptr, AlignType(Align), Mask);
79 MASKED_LOAD(Value * Ptr,unsigned Align,Value * Mask,Value * PassThru=nullptr,const Twine & Name="",Type * Ty=nullptr,MEM_CLIENT usage=MEM_CLIENT::MEM_CLIENT_INTERNAL) argument
H A Djit_pch.hpp159 typedef llvm::Align AlignType;
H A Dbuilder_gfx_mem.h71 unsigned Align,
82 virtual CallInst* MASKED_STORE(Value *Val, Value *Ptr, unsigned Align, Value *Mask, Type* Ty = nullptr, MEM_CLIENT usage = MEM_CLIENT::MEM_CLIENT_INTERNAL);
H A Dbuilder_gfx_mem.cpp324 unsigned Align,
335 return Builder::MASKED_LOAD(Ptr, Align, Mask, PassThru, Name, Ty, usage);
362 Value* Val, Value* Ptr, unsigned Align, Value* Mask, Type* Ty, MEM_CLIENT usage)
369 return Builder::MASKED_STORE(Val, Ptr, Align, Mask, Ty, usage);
323 MASKED_LOAD(Value * Ptr,unsigned Align,Value * Mask,Value * PassThru,const Twine & Name,Type * Ty,MEM_CLIENT usage) argument
361 MASKED_STORE(Value * Val,Value * Ptr,unsigned Align,Value * Mask,Type * Ty,MEM_CLIENT usage) argument
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.0.4.rst87 - anv/blorp: Align vertex buffers to 64B
88 - i965/blorp: Align vertex buffers to 64B
H A D18.2.7.rst59 - radv: Align large buffers to the fragment size.
H A D13.0.6.rst128 - swr: Align query results allocation
H A D7.10.3.rst294 - i965: Align interleaved URB write length to 2
H A D19.3.0.rst2775 - anv/block_pool: Align anv_block_pool state to 64 bits.
2781 - anv: Align fast clear color state buffer to a page.
2782 - iris: Align fast clear color state buffer to a page.
H A D20.1.0.rst1157 - tu: Align GMEM resolve blit scissor
2373 - anv: Align UBO sizes to 32B
3789 - panfrost: Align Android makefiles with recent changes
3791 - panfrost: Align Android makefiles with recent changes
H A D7.10.rst1343 - i965: Align gen6 push constant size to dispatch width.
1420 - dri/nv04: Align SIFM transfer dimensions.
H A D20.2.0.rst2973 - freedreno/fdl: Align after dividing by block size
3778 - iris: Align last_seqnos to 64 bits.
3779 - anv: Align "used" attribute to 64 bits.
H A D21.1.0.rst2460 - panfrost: Align BO size to 4096 bytes
2774 - anv: Align inline uniform data to ANV_UBO_ALIGNMENT
5398 - aco: Align NGG scratch size to 16 so a single ds_read can always read it.
H A D21.2.0.rst677 - asahi: Align strides to 16 bytes
767 - panfrost: Align NPOT divisor records
3124 - iris/bufmgr: Align vma addresses to 64K for local memory
H A D21.3.0.rst341 - pan/bi: Align staging registers on Valhall
1343 - freedreno/ir3: Align driver param upload size/offset for indirect uploads.
H A D19.0.0.rst358 - radv: Align large buffers to the fragment size.
H A D19.1.0.rst2538 - mesa: Align doubles to a 64-bit starting boundary, even if packing.
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_llvm_helper.cpp55 A->addAttr(llvm::Attribute::getWithAlignment(A->getContext(), llvm::Align(bytes)));
/xsrc/external/mit/MesaLib.old/dist/src/compiler/spirv/
H A Dspirv.core.grammar.json2705 { "kind" : "IdRef", "name" : "'Param Align'" },
2720 { "kind" : "IdRef", "name" : "'Param Align'" }
2734 { "kind" : "IdRef", "name" : "'Param Align'" }
2747 { "kind" : "IdRef", "name" : "'Param Align'" }
2760 { "kind" : "IdRef", "name" : "'Param Align'" }
3083 { "kind" : "IdRef", "name" : "'Param Align'" }
3097 { "kind" : "IdRef", "name" : "'Param Align'" }
/xsrc/external/mit/MesaLib/dist/src/compiler/spirv/
H A Dspirv.core.grammar.json3079 { "kind" : "IdRef", "name" : "'Param Align'" },
3095 { "kind" : "IdRef", "name" : "'Param Align'" }
3110 { "kind" : "IdRef", "name" : "'Param Align'" }
3124 { "kind" : "IdRef", "name" : "'Param Align'" }
3138 { "kind" : "IdRef", "name" : "'Param Align'" }
3490 { "kind" : "IdRef", "name" : "'Param Align'" }
3505 { "kind" : "IdRef", "name" : "'Param Align'" }
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json1462 "description": "asahi: Align linear texture's strides to 64 bytes",
1471 "description": "asahi: Align allocations to effective tile size",
20182 "description": "panfrost: Align instance size for IDVS",
22144 "description": "iris: Align buffer VMA to 2MiB for XeHP",
22153 "description": "anv: Align buffer VMA to 2MiB for XeHP",
30550 "description": "ac: Align ADDR_FASTCALL with addrlib",
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