| /xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/ |
| audio.c | 54 #define BIT(reg, n) BITS(reg, n, n)
132 [1] = "one bit stream",
176 if (BIT(1, 0) != 1)
178 if (BIT(0x80000000, 31) != 1)
286 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
287 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
288 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
289 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
290 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
291 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24))
[all...] |
| /xsrc/external/mit/xf86-video-tdfx/dist/src/ |
| tdfxdefs.h | 15 #define BIT(n) (1UL<<(n))
17 #define SST_SGRAM_CLK_NODELAY BIT(13)
18 #define SST_DRAM_REFRESH_EN BIT(0)
23 #define SST_SGRAM_NUM_CHIPSETS BIT(26)
26 #define SST_DISABLE_2D_BLOCK_WRITE BIT(15)
27 #define SST_MCTL_TYPE_SDRAM BIT(30)
28 #define SST_DAC_MODE_2X BIT(0)
29 #define SST_VIDEO_2X_MODE_EN BIT(26)
30 #define SST_VGA0_EXTENSIONS BIT(6)
41 #define SST_VIDEO_PROCESSOR_EN BIT(0
[all...] |
| tdfx_priv.h | 205 #define SST_EN_CMDFIFO BIT(8)
206 #define SST_CMDFIFO_AGP BIT(9)
207 #define SST_CMDFIFO_DISABLE_HOLES BIT(10)
244 #define SSTCP_PKT1_2D BIT(14)
245 #define SSTCP_INC BIT(15)
325 #define SSTCP_PKT3_PACKEDCOLOR BIT(28)
334 #define SSTCP_PKT4_2D BIT(14)
|
| tdfx_hwcurs.c | 106 pTDFX->ModeReg.vidcfg|=BIT(27);
117 pTDFX->ModeReg.vidcfg&=~BIT(27);
|
| tdfx_accel.c | 142 TDFXWriteLong(pTDFX, SST_2D_DSTBASEADDR, pTDFX->backOffset|BIT(31));
145 TDFXWriteLong(pTDFX, SST_2D_SRCBASEADDR, pTDFX->backOffset|BIT(31));
154 TDFXWriteLong(pTDFX, SST_2D_DSTBASEADDR, pTDFX->depthOffset|BIT(31));
157 TDFXWriteLong(pTDFX, SST_2D_SRCBASEADDR, pTDFX->depthOffset|BIT(31));
173 lfbmode&=~BIT(12); /* 0 bit 12 is byte swizzle */
174 lfbmode|=BIT(11); /* 1 bit 11 is word swizzle */
175 lfbmode&=~BIT(10); /* 0 bit 10 ARGB or ABGR *
[all...] |
| tdfx_driver.c | 551 banks=((dramInit0_strap&BIT(30))==0) ? 2 : 4;
686 PCI_WRITE_LONG(initbits | BIT(10), CFG_INIT_ENABLE, i);
1239 pTDFX->ModeReg.miscinit0 &= ~BIT(30); /* LFB byte swizzle */
1240 pTDFX->ModeReg.miscinit0 &= ~BIT(31); /* LFB word swizzle */
1245 pTDFX->ModeReg.miscinit0 |= BIT(30); /* LFB byte swizzle */
1246 pTDFX->ModeReg.miscinit0 |= BIT(31); /* LFB word swizzle */
1251 pTDFX->ModeReg.miscinit0 |= BIT(30); /* LFB byte swizzle */
1252 pTDFX->ModeReg.miscinit0 &= ~BIT(31); /* LFB word swizzle */
1811 tdfxReg->vgainit0 |= BIT(12);
2710 state=BIT(3)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_context.c | 148 fd_context_add_map(ctx, FD_DIRTY_VTXSTATE, BIT(FD6_GROUP_VTXSTATE));
149 fd_context_add_map(ctx, FD_DIRTY_VTXBUF, BIT(FD6_GROUP_VBO));
151 BIT(FD6_GROUP_ZSA));
153 BIT(FD6_GROUP_LRZ) | BIT(FD6_GROUP_LRZ_BINNING));
155 BIT(FD6_GROUP_PROG));
156 fd_context_add_map(ctx, FD_DIRTY_RASTERIZER, BIT(FD6_GROUP_RASTERIZER));
160 BIT(FD6_GROUP_PROG_FB_RAST));
162 BIT(FD6_GROUP_BLEND));
163 fd_context_add_map(ctx, FD_DIRTY_BLEND_COLOR, BIT(FD6_GROUP_BLEND_COLOR))
[all...] |
| fd6_draw.c | 180 ctx->gen_dirty |= BIT(FD6_GROUP_PRIMITIVE_PARAMS);
191 ctx->gen_dirty |= BIT(FD6_GROUP_PRIMITIVE_PARAMS);
199 if (!(ctx->gen_dirty & BIT(FD6_GROUP_PROG))) {
223 emit.dirty_groups |= BIT(FD6_GROUP_VS_DRIVER_PARAMS);
227 emit.dirty_groups |= BIT(FD6_GROUP_SO);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ |
| freedreno_context.h | 147 FD_DIRTY_BLEND = BIT(0),
148 FD_DIRTY_RASTERIZER = BIT(1),
149 FD_DIRTY_ZSA = BIT(2),
150 FD_DIRTY_BLEND_COLOR = BIT(3),
151 FD_DIRTY_STENCIL_REF = BIT(4),
152 FD_DIRTY_SAMPLE_MASK = BIT(5),
153 FD_DIRTY_FRAMEBUFFER = BIT(6),
154 FD_DIRTY_STIPPLE = BIT(7),
155 FD_DIRTY_VIEWPORT = BIT(8),
156 FD_DIRTY_VTXSTATE = BIT(9)
[all...] |
| freedreno_screen.h | 54 FD_GMEM_CLEARS_DEPTH_STENCIL = BIT(0),
55 FD_GMEM_DEPTH_ENABLED = BIT(1),
56 FD_GMEM_STENCIL_ENABLED = BIT(2),
57 FD_GMEM_BLEND_ENABLED = BIT(3),
58 FD_GMEM_LOGICOP_ENABLED = BIT(4),
59 FD_GMEM_FB_READ = BIT(5),
|
| freedreno_state.c | 173 so->enabled_mask |= BIT(n);
175 if (writable_bitmask & BIT(i)) {
211 mask |= BIT(n);
216 so->enabled_mask |= BIT(n);
227 so->enabled_mask &= ~BIT(n);
231 mask = (BIT(count) - 1) << start;
451 /* if scissor enable bit changed we need to mark scissor
637 mask |= BIT(n);
649 so->enabled_mask |= BIT(n);
651 so->enabled_mask &= ~BIT(n)
[all...] |
| freedreno_program.c | 40 ctx->bound_shader_stages |= BIT(shader);
42 ctx->bound_shader_stages &= ~BIT(shader);
|
| freedreno_util.h | 185 * Make the annotation a bit less verbose.. mark fields which should only
287 /* avoid losing precision on 32-bit float formats */
390 // packet types.. so freedreno_query_hw is going to need a bit of
433 #define BIT(bit) (1u << bit)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/ |
| freedreno_context.h | 118 FD_DIRTY_BLEND = BIT(0),
119 FD_DIRTY_RASTERIZER = BIT(1),
120 FD_DIRTY_ZSA = BIT(2),
121 FD_DIRTY_BLEND_COLOR = BIT(3),
122 FD_DIRTY_STENCIL_REF = BIT(4),
123 FD_DIRTY_SAMPLE_MASK = BIT(5),
124 FD_DIRTY_FRAMEBUFFER = BIT(6),
125 FD_DIRTY_STIPPLE = BIT(7),
126 FD_DIRTY_VIEWPORT = BIT(8),
127 FD_DIRTY_VTXSTATE = BIT(9)
[all...] |
| freedreno_state.c | 141 mask |= BIT(n);
148 so->enabled_mask |= BIT(n);
150 so->enabled_mask &= ~BIT(n);
153 mask = (BIT(count) - 1) << start;
190 mask |= BIT(n);
194 so->enabled_mask |= BIT(n);
196 so->enabled_mask &= ~BIT(n);
199 mask = (BIT(count) - 1) << start;
397 /* if scissor enable bit changed we need to mark scissor
553 mask |= BIT(n)
[all...] |
| freedreno_util.h | 165 /* avoid losing precision on 32-bit float formats */
416 // packet types.. so freedreno_query_hw is going to need a bit of
450 #define BIT(bit) (1u << bit)
|
| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/valhall/ |
| disassemble.h | 12 #define BIT(b) (1ull << (b))
14 #define SEXT(b, count) ((b ^ BIT(count - 1)) - BIT(count - 1))
46 /* TODO: is there a stop-bit? or does all-0's mean stop? */
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_private.h | 129 #define BIT(bit) (1u << (bit))
185 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
385 /* Currently the kernel driver uses a 32-bit GPU address space, but it
733 TU_CMD_DIRTY_VERTEX_BUFFERS = BIT(0),
734 TU_CMD_DIRTY_VB_STRIDE = BIT(1),
735 TU_CMD_DIRTY_GRAS_SU_CNTL = BIT(2),
736 TU_CMD_DIRTY_RB_DEPTH_CNTL = BIT(3),
737 TU_CMD_DIRTY_RB_STENCIL_CNTL = BIT(4)
[all...] |
| tu_nir_lower_multiview.c | 31 *mask = BIT(util_logbase2(old_mask) + 1) - 1;
|
| tu_pipeline.c | 509 /* unknown bit, seems unnecessary */
774 * a bit less ideal here..
1757 if (!(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_VB_STRIDE))) {
2236 !(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_RASTERIZER_DISCARD)))
2508 pipeline->dynamic_state_mask |= BIT(state);
2511 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2516 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_GRAS_SU_CNTL);
2520 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_GRAS_SU_CNTL);
2523 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY);
2526 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_VB_STRIDE)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/ |
| vc4_simulator_validate.h | 50 #define BIT(bit) (1u << bit)
57 test_bit(unsigned int bit, unsigned long *addr)
59 return addr[bit / BITMAP_WORDBITS] & (1ul << (bit % BITMAP_WORDBITS));
63 set_bit(unsigned int bit, unsigned long *addr)
65 return addr[bit / BITMAP_WORDBITS] |= (1ul << (bit % BITMAP_WORDBITS));
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/ |
| vc4_simulator_validate.h | 50 #define BIT(bit) (1u << bit)
57 test_bit(unsigned int bit, unsigned long *addr)
59 return addr[bit / BITMAP_WORDBITS] & (1ul << (bit % BITMAP_WORDBITS));
63 set_bit(unsigned int bit, unsigned long *addr)
65 return addr[bit / BITMAP_WORDBITS] |= (1ul << (bit % BITMAP_WORDBITS));
|
| /xsrc/external/mit/xf86-video-xgi/dist/src/ |
| vb_i2c.h | 70 // n'th bit set as 1
71 #define BIT(n) (1 << (n))
72 // n bits set as 1 from bit(0) to bit(n-1)
78 // set bits as 1 between bit(a) and bit(b)
82 // set bits as 1 between bit(a) and bit(b)
|
| /xsrc/external/mit/xorg-server.old/dist/hw/kdrive/linux/ |
| evdev.c | 40 #define ISBITSET(x,y) ((x)[LONG(y)] & BIT(y))
43 #define BIT(x) (1 << OFF(x))
|
| /xsrc/external/mit/MesaLib/dist/src/panfrost/lib/genxml/ |
| gen_pack.py | 121 /* Get the sign bit extended. */
214 (format & (1 << 21)) ? " XXX BAD BIT" : "");
337 (word, bit) = attrs["start"].split(":")
338 self.start = (int(word) * 32) + int(bit)
346 print("#error Field {} has bool type but more than one bit of size".format(self.name));
567 # Given a field (start, end) contained in word `index`, generate the 32-bit
|
