Searched refs:BITFIELD_RANGE (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/compiler/
H A Dshader_enums.h198 #define VERT_BIT_ALL BITFIELD_RANGE(0, VERT_ATTRIB_MAX)
201 #define VERT_BIT_FF_ALL BITFIELD_RANGE(0, VERT_ATTRIB_FF_MAX)
204 BITFIELD_RANGE(VERT_ATTRIB_TEX(0), VERT_ATTRIB_TEX_MAX)
208 BITFIELD_RANGE(VERT_ATTRIB_GENERIC(0), VERT_ATTRIB_GENERIC_MAX)
212 BITFIELD_RANGE(VERT_ATTRIB_MAT(0), VERT_ATTRIB_MAT_MAX)
/xsrc/external/mit/MesaLib/dist/src/compiler/
H A Dshader_enums.h240 #define VERT_BIT_ALL BITFIELD_RANGE(0, VERT_ATTRIB_MAX)
242 #define VERT_BIT_FF_ALL (BITFIELD_RANGE(0, VERT_ATTRIB_GENERIC0) | \
246 BITFIELD_RANGE(VERT_ATTRIB_TEX(0), VERT_ATTRIB_TEX_MAX)
250 BITFIELD_RANGE(VERT_ATTRIB_GENERIC(0), VERT_ATTRIB_GENERIC_MAX)
254 BITFIELD_RANGE(VERT_ATTRIB_MAT(0), VERT_ATTRIB_MAT_MAX)
/xsrc/external/mit/MesaLib.old/dist/src/util/
H A Dmacros.h305 #define BITFIELD_RANGE(b, count) \ macro
/xsrc/external/mit/MesaLib/dist/src/broadcom/simulator/
H A Dv3dx_simulator.c508 #define V3D_PCTR_0_SRC_N_MASK(x) (BITFIELD_RANGE(V3D_PCTR_0_SRC_N_SHIFT(x), \
520 uint32_t mask = BITFIELD_RANGE(0, ncounters);
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_shader_util.c488 *cu_mask &= info->chip_class == GFX10 ? ~BITFIELD_RANGE(2, 2) :
489 ~BITFIELD_RANGE(1, 1);
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Ddraw_validate.c106 BITFIELD_RANGE(max_dual_source_buffers,
H A Dblend.c258 ctx->Color._BlendUsesDualSrc |= BITFIELD_RANGE(1, numBuffers - 1);
/xsrc/external/mit/MesaLib/dist/src/util/
H A Dmacros.h392 #define BITFIELD_RANGE(b, count) \ macro
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_gather_info.c449 BITFIELD_RANGE(semantics.location - VARYING_SLOT_VAR0_16BIT, num_slots);
853 BITFIELD_RANGE(shader->info.num_images, num_image_slots);
857 BITFIELD_RANGE(shader->info.num_images, num_image_slots);
H A Dnir.c98 new_mask |= BITFIELD_RANGE(start, count);
H A Dnir_lower_io.c475 BITFIELD_RANGE(src_comp, num_comps));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dzink_context.c3787 rebind_mask & BITFIELD_RANGE(TC_BINDING_UBO_VS, PIPE_SHADER_TYPES) :
3788 ((res->ubo_bind_count[0] ? BITFIELD_RANGE(TC_BINDING_UBO_VS, (PIPE_SHADER_TYPES - 1)) : 0) |
3798 rebind_mask &= ~BITFIELD_RANGE(TC_BINDING_UBO_VS, PIPE_SHADER_TYPES);
3803 rebind_mask & BITFIELD_RANGE(TC_BINDING_SSBO_VS, PIPE_SHADER_TYPES) :
3804 BITFIELD_RANGE(TC_BINDING_SSBO_VS, PIPE_SHADER_TYPES);
3815 rebind_mask &= ~BITFIELD_RANGE(TC_BINDING_SSBO_VS, PIPE_SHADER_TYPES);
3819 rebind_mask & BITFIELD_RANGE(TC_BINDING_SAMPLERVIEW_VS, PIPE_SHADER_TYPES) :
3820 BITFIELD_RANGE(TC_BINDING_SAMPLERVIEW_VS, PIPE_SHADER_TYPES);
3830 rebind_mask &= ~BITFIELD_RANGE(TC_BINDING_SAMPLERVIEW_VS, PIPE_SHADER_TYPES);
3835 rebind_mask & BITFIELD_RANGE(TC_BINDING_IMAGE_V
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_shader_llvm_vs.c408 if (!(clipdist_mask & BITFIELD_RANGE(reg_index * 4, 4)))
608 if (clipdist_mask & BITFIELD_RANGE(index * 4, 4)) {
H A Dsi_descriptors.c598 unbound_mask |= BITFIELD_RANGE(start_slot + count, unbind_num_trailing_slots);
/xsrc/external/mit/MesaLib/dist/src/intel/dev/
H A Dintel_device_info.c1089 const unsigned ppipe_mask = BITFIELD_RANGE(p * ppipe_bits, ppipe_bits);
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_pipeline.c837 if (!(stage->key.wm.color_outputs_valid & BITFIELD_RANGE(rt, array_len))) {
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_pipeline.c1149 BITFIELD_RANGE(rt, array_len))) {
1175 stage->key.wm.color_outputs_valid |= BITFIELD_RANGE(rt, array_len);
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/util/
H A Du_threaded_context.c1524 tc->image_buffers_writeable_mask[shader] &= ~BITFIELD_RANGE(start, count);
1607 tc->shader_buffers_writeable_mask[shader] &= ~BITFIELD_RANGE(start, count);
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dnir_to_vir.c378 BITFIELD_RANGE(first_component, *tmu_writes);

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