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Searched refs:BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (Results 1 - 5 of 5) sorted by relevancy

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
i965_reg.h	`437 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)`
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
i965_reg.h	`410 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)`
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
i965_reg.h	`437 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)`
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
i965_reg.h	`410 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)`
/xsrc/external/mit/xf86-video-intel-old/dist/src/
i810_reg.h	`2751 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)`

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