HomeSort by: relevance | last modified time | path
    Searched refs:BUSY (Results 1 - 3 of 3) sorted by relevancy

  /xsrc/external/mit/xf86-video-i128/dist/src/
i128accel.c 67 #define ENG_PIPELINE_READY() { while (pI128->mem.rbase_a[BUSY] & BUSY_BUSY) ; }
i128exa.c 51 while (pI128->mem.rbase_a[BUSY] & BUSY_BUSY)
i128reg.h 206 #define FLOW_DEB 0x01 /* drawing engine busy */
207 #define FLOW_MCB 0x02 /* mem controller busy */
210 #define BUSY 0x000C/4
211 #define BUSY_BUSY 0x01 /* command pipeline busy */

Completed in 5 milliseconds