1/* 2 * Copyright 1994 by Robin Cutshaw <robin@XFree86.Org> 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of Robin Cutshaw not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. Robin Cutshaw makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * ROBIN CUTSHAW DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL ROBIN CUTSHAW BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 * 22 */ 23 24#ifndef I128REG_H 25#define I128REG_H 26 27#include "xf86Pci.h" 28 29struct i128pci { 30 CARD32 devicevendor; 31 CARD32 statuscommand; 32 CARD32 classrev; 33 CARD32 bhlc; 34 CARD32 base0; 35 CARD32 base1; 36 CARD32 base2; 37 CARD32 base3; 38 CARD32 base4; 39 CARD32 base5; 40 CARD32 rsvd0; 41 CARD32 rsvd1; 42 CARD32 baserom; 43 CARD32 rsvd2; 44 CARD32 rsvd3; 45 CARD32 lgii; 46}; 47 48struct i128io { 49 CARD32 rbase_g; 50 CARD32 rbase_w; 51 CARD32 rbase_a; 52 CARD32 rbase_b; 53 CARD32 rbase_i; 54 CARD32 rbase_e; 55 CARD32 id; 56 CARD32 config1; 57 CARD32 config2; 58 CARD32 sgram; 59 CARD32 soft_sw; 60 CARD32 vga_ctl; 61}; 62 63struct i128mem { 64 unsigned char *mw0_ad; 65 unsigned char *mw1_ad; 66 unsigned char *xyw_ada; 67 unsigned char *xyw_adb; 68 CARD32 *rbase_g; 69 CARD32 *rbase_w; 70 CARD32 *rbase_a; 71 CARD32 *rbase_b; 72 CARD32 *rbase_i; 73 float *rbase_af; 74}; 75 76/* save the registers needed for restoration in this structure */ 77typedef struct { 78 unsigned long iobase; /* saved only for iobase indexing */ 79 CARD32 config1; /* iobase+0x1C register */ 80 CARD32 config2; /* iobase+0x20 register */ 81 CARD32 sgram; /* iobase+0x24 register */ 82 CARD32 vga_ctl; /* iobase+0x30 register */ 83 CARD32 i128_base_g[0x60/4]; /* base g registers */ 84 CARD32 i128_base_w[0x28/4]; /* base w registers */ 85 CARD32 intm; /* base a+0x04 register */ 86 unsigned char Ti302X[0x40]; /* Ti302[05] registers */ 87 unsigned char Ti3025[9]; /* Ti3025 N,M,P for PCLK, MCLK, LCLK */ 88 unsigned char IBMRGB[0x101]; /* IBMRGB registers */ 89} I128RegRec, *I128RegPtr; 90 91 92/* display list processor instruction formats */ 93typedef union { 94 struct { 95 CARD8 aad; 96 CARD8 bad; 97 CARD8 cad; 98 CARD8 control; 99 CARD32 rad; 100 CARD32 rbd; 101 CARD32 rcd; 102 } f0; 103 struct { 104 CARD32 xy0; 105 CARD32 xy2; 106 CARD32 xy3; 107 CARD32 xy1; 108 } f1; 109 CARD32 f4[4]; 110} I128dlpu; 111 112#define UNKNOWN_DAC -1 113#define TI3025_DAC 0 114#define IBM524_DAC 1 115#define IBM526_DAC 2 116#define IBM528_DAC 3 117#define SILVER_HAMMER_DAC 4 118 119#define I128_MEMORY_UNKNOWN 0x01 120#define I128_MEMORY_DRAM 0x02 121#define I128_MEMORY_WRAM 0x04 122#define I128_MEMORY_SGRAM 0x08 123 124/* RBASE_I register offsets */ 125 126#define GINTP 0x0000 127#define GINTM 0x0004 128#define SGRAM 0x00A4 129 130/* DMA regs, relative to RBASE_I. T2R4 only. */ 131#define DMA_SRC 0x00D0/4 132#define DMA_SRC_MASK 0x07 133#define DMA_DST 0x00D4/4 134#define DMA_DST_MASK 0xFC000007 135#define DMA_CMD 0x00D8/4 136#define DMA_QWORDS_MASK 0x0001FFFF 137#define DMA_REQ_LENGTH_4Q 0x00000000 138#define DMA_REQ_LENGTH_8Q 0x01000000 139#define DMA_REQ_LENGTH_16Q 0x02000000 140#define DMA_REQ_LENGTH_32Q 0x03000000 141#define DMA_PIPELINE_READY 0x10000000 142#define DMA_IDLE 0x20000000 143#define DMA_EXPEDITE 0x40000000 144 145/* RBASE_G register offsets (divided by four for double word indexing */ 146 147#define WR_ADR 0x0000/4 148#define PAL_DAT 0x0004/4 149#define PEL_MASK 0x0008/4 150#define RD_ADR 0x000C/4 151#define INDEX_TI 0x0018/4 /* TI ramdac */ 152#define DATA_TI 0x001C/4 /* TI ramdac */ 153#define IDXL_I 0x0010/4 /* IBM ramdac */ 154#define IDXH_I 0x0014/4 /* IBM ramdac */ 155#define DATA_I 0x0018/4 /* IBM ramdac */ 156#define IDXCTL_I 0x001C/4 /* IBM ramdac */ 157#define INT_VCNT 0x0020/4 158#define INT_HCNT 0x0024/4 159#define DB_ADR 0x0028/4 160#define DB_PTCH 0x002C/4 161#define CRT_HAC 0x0030/4 162#define CRT_HBL 0x0034/4 163#define CRT_HFP 0x0038/4 164#define CRT_HS 0x003C/4 165#define CRT_VAC 0x0040/4 166#define CRT_VBL 0x0044/4 167#define CRT_VFP 0x0048/4 168#define CRT_VS 0x004C/4 169#define CRT_LCNT 0x0050/4 170#define CRT_ZOOM 0x0054/4 171#define CRT_1CON 0x0058/4 172#define CRT_2CON 0x005C/4 173 174 175/* RBASE_W register offsets (divided by four for double word indexing */ 176/* MW1_* are probably T2R and T2R4 only */ 177 178#define MW0_CTRL 0x0000/4 179#define MW0_AD 0x0004/4 180#define MW0_SZ 0x0008/4 /* 2MB = 0x9, 4MB = 0xA, 8MB = 0xB */ 181#define MW0_PGE 0x000C/4 182#define MW0_ORG 0x0010/4 183#define MW0_MSRC 0x0018/4 184#define MW0_WKEY 0x001C/4 185#define MW0_KDAT 0x0020/4 186#define MW0_MASK 0x0024/4 187#define MW1_CTRL 0x0028/4 188#define MW1_AD 0x002C/4 189#define MW1_SZ 0x0030/4 190#define MW1_PGE 0x0034/4 191#define MW1_ORG 0x0038/4 192#define MW1_MSRC 0x0040/4 193#define MW1_WKEY 0x0044/4 194#define MW1_KDAT 0x0048/4 195#define MW1_MASK 0x004C/4 196 197/* RBASE_[AB] register offsets (divided by four for double word indexing */ 198 199#define INTP 0x0000/4 200#define INTP_DD_INT 0x01 /* drawing op completed */ 201#define INTP_CL_INT 0x02 202#define INTM 0x0004/4 203#define INTM_DD_MSK 0x01 204#define INTM_CL_MSK 0x02 205#define FLOW 0x0008/4 206#define FLOW_DEB 0x01 /* drawing engine busy */ 207#define FLOW_MCB 0x02 /* mem controller busy */ 208#define FLOW_CLP 0x04 209#define FLOW_PRV 0x08 /* prev cmd still running or cache ready */ 210#define BUSY 0x000C/4 211#define BUSY_BUSY 0x01 /* command pipeline busy */ 212#define XYW_AD 0x0010/4 213#define Z_CTRL 0x0018/4 214#define BUF_CTRL 0x0020/4 215#define BC_AMV 0x02 216#define BC_MP 0x04 217#define BC_AMD 0x08 218#define BC_SEN_MSK 0x0300 219#define BC_SEN_DB 0x0000 220#define BC_SEN_VB 0x0100 221#define BC_SEN_MB 0x0200 222#define BC_SEN_CB 0x0300 223#define BC_DEN_MSK 0x0C00 224#define BC_DEN_DB 0x0000 225#define BC_DEN_VB 0x0400 226#define BC_DEN_MB 0x0800 227#define BC_DEN_CB 0x0C00 228#define BC_DSE 0x1000 229#define BC_VSE 0x2000 230#define BC_MSE 0x4000 231#define BC_PS_MSK 0x001F0000 232#define BC_MDM_MSK 0x00600000 233#define BC_MDM_KEY 0x00200000 234#define BC_MDM_PLN 0x00400000 235#define BC_BLK_ENA 0x00800000 236#define BC_PSIZ_MSK 0x03000000 237#define BC_PSIZ_8B 0x00000000 238#define BC_PSIZ_16B 0x01000000 239#define BC_PSIZ_32B 0x02000000 240#define BC_PSIZ_NOB 0x03000000 241#define BC_CO 0x40000000 242#define BC_CR 0x80000000 243#define DE_PGE 0x0024/4 244#define DP_DVP_MSK 0x0000001F 245#define DP_MP_MSK 0x000F0000 246#define DE_SORG 0x0028/4 247#define DE_DORG 0x002C/4 248#define DE_MSRC 0x0030/4 249/* these next two sound bogus */ 250#define DE_WKEY 0x0038/4 251#define DE_KYDAT 0x003C/4 252#define DE_TPTCH 0x0038/4 253#define DE_ZPTCH 0x003C/4 254#define DE_SPTCH 0x0040/4 255#define DE_DPTCH 0x0044/4 256#define CMD 0x0048/4 257#define CMD_OPC_MSK 0x000000FF 258#define CMD_ROP_MSK 0x0000FF00 259#define CMD_STL_MSK 0x001F0000 260#define CMD_CLP_MSK 0x00E00000 261#define CMD_PAT_MSK 0x0F000000 262#define CMD_HDF_MSK 0x70000000 263#define CMD_OPC 0x0050/4 264#define CO_NOOP 0x00 265#define CO_BITBLT 0x01 266#define CO_LINE 0x02 267#define CO_ELINE 0x03 268#define CO_TRIAN 0x04 269#define CO_PLINE 0x05 270#define CO_RXFER 0x06 271#define CO_WXFER 0x07 272#define CO_LINE3D 0x08 273#define CO_TRIAN3D 0x09 274#define CO_TEXINV 0x0A 275#define CO_LOADPAL 0x0B 276#define CMD_ROP 0x0054/4 277#define CR_CLEAR 0x00 278#define CR_NOR 0x01 279#define CR_AND_INV 0x02 280#define CR_COPY_INV 0x03 281#define CR_AND_REV 0x04 282#define CR_INVERT 0x05 283#define CR_XOR 0x06 284#define CR_NAND 0x07 285#define CR_AND 0x08 286#define CR_EQUIV 0x09 287#define CR_NOOP 0x0A 288#define CR_OR_INV 0x0B 289#define CR_COPY 0x0C 290#define CR_OR_REV 0x0D 291#define CR_OR 0x0E 292#define CR_SET 0x0F 293#define CMD_STYLE 0x0058/4 294#define CS_SOLID 0x01 295#define CS_TRNSP 0x02 296#define CS_STP_NO 0x00 297#define CS_STP_PL 0x04 298#define CS_STP_PA32 0x08 299#define CS_STP_PA8 0x0C 300#define CS_EDI 0x10 301#define CMD_PATRN 0x005C/4 302#define CP_APAT_NO 0x00 303#define CP_APAT_8X 0x01 304#define CP_APAT_32X 0x02 305#define CP_NLST 0x04 306#define CP_PRST 0x08 307#define CMD_CLP 0x0060/4 308#define CC_NOCLP 0x00 309#define CC_CLPRECI 0x02 310#define CC_CLPRECO 0x03 311#define CC_CLPSTOP 0x04 312#define CMD_HDF 0x0064/4 313#define CH_BIT_SWP 0x01 314#define CH_BYT_SWP 0x02 315#define CH_WRD_SWP 0x04 316#define FORE 0x0068/4 317#define BACK 0x006C/4 318#define MASK 0x0070/4 319#define RMSK 0x0074/4 320#define LPAT 0x0078/4 321#define PCTRL 0x007C/4 322#define PC_PLEN_MSK 0x0000001F 323#define PC_PSCL_MSK 0x000000E0 324#define PC_SPTR_MSK 0x00001F00 325#define PC_SSCL_MSK 0x0000E000 326#define PC_STATE_MSK 0xFFFF0000 327#define CLPTL 0x0080/4 328#define CLPTLY_MSK 0x0000FFFF 329#define CLPTLX_MSK 0xFFFF0000 330#define CLPBR 0x0084/4 331#define CLPBRY_MSK 0x0000FFFF 332#define CLPBRX_MSK 0xFFFF0000 333#define XY0_SRC 0x0088/4 334#define XY1_DST 0x008C/4 /* trigger */ 335#define XY2_WH 0x0090/4 336#define XY3_DIR 0x0094/4 337#define DIR_LR_TB 0x00000000 338#define DIR_LR_BT 0x00000001 339#define DIR_RL_TB 0x00000002 340#define DIR_RL_BT 0x00000003 341#define XY4_ZM 0x0098/4 342#define ZOOM_NONE 0x00000000 343#define XY_Y_DATA 0x0000FFFF 344#define XY_X_DATA 0xFFFF0000 345#define XY_I_DATA1 0x0000FFFF 346#define XY_I_DATA2 0xFFFF0000 347#define LOD0_ORG 0x00D0/4 348#define LOD1_ORG 0x00D4/4 349#define LOD2_ORG 0x00D8/4 350#define LOD3_ORG 0x00DC/4 351#define LOD4_ORG 0x00E0/4 352#define LOD5_ORG 0x00E4/4 353#define LOD6_ORG 0x00E8/4 354#define LOD7_ORG 0x00EC/4 355#define LOD8_ORG 0x00F0/4 356#define LOD9_ORG 0x00F4/4 357 358#define DL_ADR 0x00F8/4 359#define DL_CNTRL 0x00FC/4 360#define ACNTRL 0x016C/4 361#define ASRC_FUNC 0x0000000F 362#define ADST_FUNC 0x000000F0 363#define ACTL_SRE 0x00000100 /* 0: pixel alpha, 1: srca reg */ 364#define ACTL_DRE 0x00000200 /* likewise */ 365#define ACTL_BE 0x00000400 366#define ACTL_AOP 0x000F0000 367#define ACTL_AEN 0x00100000 /* alpha compare enable */ 368#define ACTL_ASL 0x01000000 /* 0: texture alpha, 1: vertex alpha */ 369#define ACTL_AMD 0x02000000 370#define ACTL_DAB 0x04000000 371#define THREEDCTL 0x0170/4 372#define TCTL_ZE 0x00000001 373#define TCTL_ZRO 0x00000002 374#define TCTL_FIS 0x00000008 375#define TCTL_FSL 0x00000010 376#define TCTL_ZOP 0x000000E0 377#define TCTL_ZOP_SHIFT 5 378#define TCTL_YOP 0x00000800 379#define TCTL_HOP 0x00003100 380#define TCTL_KYP 0x00004000 381#define TCTL_KYE 0x00008000 382#define TCTL_DOP 0x00010000 383#define TCTL_ABS 0x00020000 384#define TCTL_TBS 0x00040000 385#define TCTL_RSL 0x00080000 386#define TCTL_SSC 0x00200000 387#define TCTL_CW 0x00400000 388#define TCTL_BCE 0x00800000 389#define TCTL_SH 0x01000000 390#define TCTL_SPE 0x02000000 391#define TCTL_RSC 0x04000000 392#define TCTL_FEN 0x08000000 393#define TCTL_RT 0x10000000 394#define TCTL_P8 0x20000000 395#define TCTL_ZS 0x40000000 396#define TEX_CTL 0x0174/4 397#define TEX_TM 0x00000001 398#define TEX_MM 0x00000002 399#define TEX_NMG 0x00000004 400#define TEX_MLM 0x00000008 401#define TEX_NMN 0x00000010 402#define TEX_RM 0x00000020 403#define TEX_PM 0x00000040 404#define TEX_CCS 0x00000080 405#define TEX_TCU 0x00000100 406#define TEX_TCV 0x00000200 407#define TEX_MLP2 0x00000400 408#define TEX_MMN 0x0000F000 409#define TEX_MMSIZEX 0x000F0000 410#define TEX_MMSIZEY 0x00F00000 411#define TEX_FMT 0x3F000000 412#define TEX_TCT 0x40000000 413#define TEX_UVS 0x80000000 414#define PPTR 0x0178/4 415/* for each vertex: x, y, z, w, color, specular color, u, v */ 416#define V0_X 0x017C/4 417#define V0_Y 0x0180/4 418#define V0_Z 0x0184/4 419#define V0_W 0x0188/4 420#define V0_C 0x018C/4 421#define V0_S 0x0190/4 422#define V0_U 0x0194/4 423#define V0_V 0x0198/4 424#define V1_X 0x019C/4 425#define V1_Y 0x01A0/4 426#define V1_Z 0x01A4/4 427#define V1_W 0x01A8/4 428#define V1_C 0x01AC/4 429#define V1_S 0x01B0/4 430#define V1_U 0x01B4/4 431#define V1_V 0x01B8/4 432#define V2_X 0x01BC/4 433#define V2_Y 0x01C0/4 434#define V2_Z 0x01C4/4 435#define V2_W 0x01C8/4 436#define V2_C 0x01CC/4 437#define V2_S 0x01D0/4 438#define V2_U 0x01D4/4 439#define V2_V 0x01D8/4 440#define TRIGGER3D 0x01DC/4 441 442/* alpha blend functions */ 443#define ABLEND_SRC_ZERO 0 444#define ABLEND_SRC_ONE 1 445#define ABLEND_SRC_DST_COLOR 2 446#define ABLEND_SRC_OMDST_COLOR 3 447#define ABLEND_SRC_SRC_ALPHA 4 448#define ABLEND_SRC_OMSRC_ALPHA 5 449#define ABLEND_SRC_DST_ALPHA 6 450#define ABLEND_SRC_OMDST_ALPHA 7 451#define ABLEND_DST_ZERO 0 << 4 452#define ABLEND_DST_ONE 1 << 4 453#define ABLEND_DST_SRC_COLOR 2 << 4 454#define ABLEND_DST_OMSRC_COLOR 3 << 4 455#define ABLEND_DST_SRC_ALPHA 4 << 4 456#define ABLEND_DST_OMSRC_ALPHA 5 << 4 457#define ABLEND_DST_DST_ALPHA 6 << 4 458#define ABLEND_DST_OMDST_ALPHA 7 << 4 459 460/* comparison functions */ 461#define COMP_FALSE 0 462#define COMP_TRUE 1 463#define COMP_LT 2 464#define COMP_LE 3 465#define COMP_EQ 4 466#define COMP_GE 5 467#define COMP_GT 6 468#define COMP_NE 7 469 470 471#define I128_WAIT_READY 1 472#define I128_WAIT_DONE 2 473 474typedef struct { 475 unsigned char r, b, g; 476} LUTENTRY; 477 478#define RGB8_PSEUDO (-1) 479#define RGB16_565 0 480#define RGB16_555 1 481#define RGB32_888 2 482 483#define MB mem_barrier() 484 485 486/* TI ramdac indirect indexed registers */ 487 488#define TI_CURS_X_LOW 0x00 489#define TI_CURS_X_HIGH 0x01 /* only lower 4 bits are used */ 490#define TI_CURS_Y_LOW 0x02 491#define TI_CURS_Y_HIGH 0x03 /* only lower 4 bits are used */ 492#define TI_SPRITE_ORIGIN_X 0x04 493#define TI_SPRITE_ORIGIN_Y 0x05 494#define TI_CURS_CONTROL 0x06 495#define TI_PLANAR_ACCESS 0x80 /* 3025 only - 80 == BT485 mode */ 496#define TI_CURS_SPRITE_ENABLE 0x40 497#define TI_CURS_X_WINDOW_MODE 0x10 498#define TI_CURS_CTRL_MASK (TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE) 499#define TI_CURS_RAM_ADDR_LOW 0x08 500#define TI_CURS_RAM_ADDR_HIGH 0x09 501#define TI_CURS_RAM_DATA 0x0A 502#define TI_TRUE_COLOR_CONTROL 0x0E /* 3025 only */ 503#define TI_TC_BTMODE 0x04 /* on = BT485 mode, off = TI3020 mode */ 504#define TI_TC_NONVGAMODE 0x02 /* on = nonvgamode, off = vgamode */ 505#define TI_TC_8BIT 0x01 /* on = 8/4bit, off = 16/32bit */ 506#define TI_VGA_SWITCH_CONTROL 0x0F /* 3025 only */ 507#define TI_LATCH_CONTROL 0x0F /* 3026 only */ 508#define TI_WINDOW_START_X_LOW 0x10 509#define TI_WINDOW_START_X_HIGH 0x11 510#define TI_WINDOW_STOP_X_LOW 0x12 511#define TI_WINDOW_STOP_X_HIGH 0x13 512#define TI_WINDOW_START_Y_LOW 0x14 513#define TI_WINDOW_START_Y_HIGH 0x15 514#define TI_WINDOW_STOP_Y_LOW 0x16 515#define TI_WINDOW_STOP_Y_HIGH 0x17 516#define TI_MUX_CONTROL_1 0x18 517#define TI_MUX1_PSEUDO_COLOR 0x80 518#define TI_MUX1_DIRECT_888 0x06 519#define TI_MUX1_DIRECT_565 0x05 520#define TI_MUX1_DIRECT_555 0x04 521#define TI_MUX1_DIRECT_664 0x03 522#define TI_MUX1_TRUE_888 0x46 523#define TI_MUX1_TRUE_565 0x45 524#define TI_MUX1_TRUE_555 0x44 525#define TI_MUX1_TRUE_664 0x43 526#define TI_MUX1_3025D_888 0x0E /* 3025 only */ 527#define TI_MUX1_3025D_565 0x0D /* 3025 only */ 528#define TI_MUX1_3025D_555 0x0C /* 3025 only */ 529#define TI_MUX1_3025T_888 0x4E /* 3025 only */ 530#define TI_MUX1_3025T_565 0x4D /* 3025 only */ 531#define TI_MUX1_3025T_555 0x4C /* 3025 only */ 532#define TI_MUX1_3026D_888 0x06 /* 3026 only */ 533#define TI_MUX1_3026D_565 0x05 /* 3026 only */ 534#define TI_MUX1_3026D_555 0x04 /* 3026 only */ 535#define TI_MUX1_3026D_888_P8 0x16 /* 3026 only */ 536#define TI_MUX1_3026D_888_P5 0x1e /* 3026 only */ 537#define TI_MUX1_3026T_888 0x46 /* 3026 only */ 538#define TI_MUX1_3026T_565 0x45 /* 3026 only */ 539#define TI_MUX1_3026T_555 0x44 /* 3026 only */ 540#define TI_MUX1_3026T_888_P8 0x56 /* 3026 only */ 541#define TI_MUX1_3026T_888_P5 0x5e /* 3026 only */ 542#define TI_MUX_CONTROL_2 0x19 543#define TI_MUX2_BUS_VGA 0x98 544#define TI_MUX2_BUS_PC_D8P64 0x1C 545#define TI_MUX2_BUS_DC_D24P64 0x1C 546#define TI_MUX2_BUS_DC_D16P64 0x04 547#define TI_MUX2_BUS_DC_D15P64 0x04 548#define TI_MUX2_BUS_TC_D24P64 0x04 549#define TI_MUX2_BUS_TC_D16P64 0x04 550#define TI_MUX2_BUS_TC_D15P64 0x04 551#define TI_MUX2_BUS_3026PC_D8P64 0x4C 552#define TI_MUX2_BUS_3026DC_D24P64 0x5C 553#define TI_MUX2_BUS_3026DC_D16P64 0x54 554#define TI_MUX2_BUS_3026DC_D15P64 0x54 555#define TI_MUX2_BUS_3026TC_D24P64 0x5c 556#define TI_MUX2_BUS_3026TC_D16P64 0x54 557#define TI_MUX2_BUS_3026TC_D15P64 0x54 558#define TI_MUX2_BUS_3030PC_D8P128 0x4d 559#define TI_MUX2_BUS_3030DC_D24P128 0x5d 560#define TI_MUX2_BUS_3030DC_D16P128 0x55 561#define TI_MUX2_BUS_3030DC_D15P128 0x55 562#define TI_MUX2_BUS_3030TC_D24P128 0x5d 563#define TI_MUX2_BUS_3030TC_D16P128 0x55 564#define TI_MUX2_BUS_3030TC_D15P128 0x55 565#define TI_INPUT_CLOCK_SELECT 0x1A 566#define TI_ICLK_CLK0 0x00 567#define TI_ICLK_CLK0_DOUBLE 0x10 568#define TI_ICLK_CLK1 0x01 569#define TI_ICLK_CLK1_DOUBLE 0x11 570#define TI_ICLK_CLK2 0x02 /* 3025 only */ 571#define TI_ICLK_CLK2_DOUBLE 0x12 /* 3025 only */ 572#define TI_ICLK_CLK2_I 0x03 /* 3025 only */ 573#define TI_ICLK_CLK2_I_DOUBLE 0x13 /* 3025 only */ 574#define TI_ICLK_CLK2_E 0x04 /* 3025 only */ 575#define TI_ICLK_CLK2_E_DOUBLE 0x14 /* 3025 only */ 576#define TI_ICLK_PLL 0x05 /* 3025 only */ 577#define TI_OUTPUT_CLOCK_SELECT 0x1B 578#define TI_OCLK_VGA 0x3E 579#define TI_OCLK_S 0x40 580#define TI_OCLK_NS 0x80 /* 3025 only */ 581#define TI_OCLK_V1 0x00 582#define TI_OCLK_V2 0x08 583#define TI_OCLK_V4 0x10 584#define TI_OCLK_V8 0x18 585#define TI_OCLK_R1 0x00 586#define TI_OCLK_R2 0x01 587#define TI_OCLK_R4 0x02 588#define TI_OCLK_R8 0x03 589#define TI_OCLK_S_V1_R8 (TI_OCLK_S | TI_OCLK_V1 | TI_OCLK_R8) 590#define TI_OCLK_S_V2_R8 (TI_OCLK_S | TI_OCLK_V2 | TI_OCLK_R8) 591#define TI_OCLK_S_V4_R8 (TI_OCLK_S | TI_OCLK_V4 | TI_OCLK_R8) 592#define TI_OCLK_S_V8_R8 (TI_OCLK_S | TI_OCLK_V8 | TI_OCLK_R8) 593#define TI_OCLK_S_V2_R4 (TI_OCLK_S | TI_OCLK_V2 | TI_OCLK_R4) 594#define TI_OCLK_S_V4_R4 (TI_OCLK_S | TI_OCLK_V4 | TI_OCLK_R4) 595#define TI_OCLK_S_V1_R2 (TI_OCLK_S | TI_OCLK_V1 | TI_OCLK_R2) 596#define TI_OCLK_S_V2_R2 (TI_OCLK_S | TI_OCLK_V2 | TI_OCLK_R2) 597#define TI_OCLK_NS_V1_R1 (TI_OCLK_NS | TI_OCLK_V1 | TI_OCLK_R1) 598#define TI_OCLK_NS_V2_R2 (TI_OCLK_NS | TI_OCLK_V2 | TI_OCLK_R2) 599#define TI_OCLK_NS_V4_R4 (TI_OCLK_NS | TI_OCLK_V4 | TI_OCLK_R4) 600#define TI_PALETTE_PAGE 0x1C 601#define TI_GENERAL_CONTROL 0x1D 602#define TI_MISC_CONTROL 0x1E /* 3025 only */ 603#define TI_MC_POWER_DOWN 0x01 604#define TI_MC_DOTCLK_DISABLE 0x02 605#define TI_MC_INT_6_8_CONTROL 0x04 /* 00 == external 6/8 pin */ 606#define TI_MC_8_BPP 0x08 /* 00 == 6bpp */ 607#define TI_MC_PSEL_POLARITY 0x20 /* 3026 only, PSEL polarity select */ 608#define TI_MC_VCLK_POLARITY 0x20 609#define TI_MC_LCLK_LATCH 0x40 /* VCLK == 00, default */ 610#define TI_MC_LOOP_PLL_RCLK 0x80 611#define TI_OVERSCAN_COLOR_RED 0x20 612#define TI_OVERSCAN_COLOR_GREEN 0x21 613#define TI_OVERSCAN_COLOR_BLUE 0x22 614#define TI_CURSOR_COLOR_0_RED 0x23 615#define TI_CURSOR_COLOR_0_GREEN 0x24 616#define TI_CURSOR_COLOR_0_BLUE 0x25 617#define TI_CURSOR_COLOR_1_RED 0x26 618#define TI_CURSOR_COLOR_1_GREEN 0x27 619#define TI_CURSOR_COLOR_1_BLUE 0x28 620#define TI_AUXILIARY_CONTROL 0x29 621#define TI_AUX_SELF_CLOCK 0x08 622#define TI_AUX_W_CMPL 0x01 623#define TI_GENERAL_IO_CONTROL 0x2A 624#define TI_GIC_ALL_BITS 0x1F 625#define TI_GENERAL_IO_DATA 0x2B 626#define TI_GID_W2000_6BIT 0x00 627#define TI_GID_N9_964 0x01 628#define TI_GID_ELSA_SOG 0x04 629#define TI_GID_W2000_8BIT 0x08 630#define TI_GID_S3_DAC_6BIT 0x1C 631#define TI_GID_S3_DAC_8BIT 0x1E 632#define TI_GID_TI_DAC_6BIT 0x1D 633#define TI_GID_TI_DAC_8BIT 0x1F 634#define TI_PLL_CONTROL 0x2C /* 3025 only */ 635#define TI_PIXEL_CLOCK_PLL_DATA 0x2D /* 3025 only */ 636#define TI_PLL_ENABLE 0x08 /* 3025 only */ 637#define TI_MCLK_PLL_DATA 0x2E /* 3025 only */ 638#define TI_LOOP_CLOCK_PLL_DATA 0x2F /* 3025 only */ 639#define TI_COLOR_KEY_OLVGA_LOW 0x30 640#define TI_COLOR_KEY_OLVGA_HIGH 0x31 641#define TI_COLOR_KEY_RED_LOW 0x32 642#define TI_COLOR_KEY_RED_HIGH 0x33 643#define TI_COLOR_KEY_GREEN_LOW 0x34 644#define TI_COLOR_KEY_GREEN_HIGH 0x35 645#define TI_COLOR_KEY_BLUE_LOW 0x36 646#define TI_COLOR_KEY_BLUE_HIGH 0x37 647#define TI_COLOR_KEY_CONTROL 0x38 648#define TI_COLOR_KEY_CMPL 0x10 649#define TI_MCLK_DCLK_CONTROL 0x39 /* 3025 only */ 650#define TI_MCLK_LCLK_CONTROL 0x39 /* 3026 only */ 651#define TI_SENSE_TEST 0x3A 652#define TI_TEST_DATA 0x3B 653#define TI_CRC_LOW 0x3C 654#define TI_CRC_HIGH 0x3D 655#define TI_CRC_CONTROL 0x3E 656#define TI_ID 0x3F 657#define TI_VIEWPOINT20_ID 0x20 658#define TI_VIEWPOINT25_ID 0x25 659#define TI_MODE_85_CONTROL 0xD5 /* 3025 only */ 660 661#define TI_REF_FREQ 14.31818 /* 3025 only */ 662 663/* 664 * which clocks should be set (just flags...) 665 */ 666#define TI_BOTH_CLOCKS 1 667#define TI_LOOP_CLOCK 2 668 669/* IBM ramdac registers */ 670 671#define IBMRGB_rev 0x00 672#define IBMRGB_id 0x01 673#define IBMRGB_misc_clock 0x02 674#define IBMRGB_sync 0x03 675#define IBMRGB_hsync_pos 0x04 676#define IBMRGB_pwr_mgmt 0x05 677#define IBMRGB_dac_op 0x06 678#define IBMRGB_pal_ctrl 0x07 679#define IBMRGB_sysclk 0x08 /* not RGB525 */ 680#define IBMRGB_pix_fmt 0x0a 681#define IBMRGB_8bpp 0x0b 682#define IBMRGB_16bpp 0x0c 683#define IBMRGB_24bpp 0x0d 684#define IBMRGB_32bpp 0x0e 685#define IBMRGB_pll_ctrl1 0x10 686#define IBMRGB_pll_ctrl2 0x11 687#define IBMRGB_pll_ref_div_fix 0x14 688#define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */ 689#define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */ 690#define IBMRGB_f0 0x20 691#define IBMRGB_m0 0x20 692#define IBMRGB_n0 0x21 693#define IBMRGB_curs 0x30 694#define IBMRGB_curs_xl 0x31 695#define IBMRGB_curs_xh 0x32 696#define IBMRGB_curs_yl 0x33 697#define IBMRGB_curs_yh 0x34 698#define IBMRGB_curs_hot_x 0x35 699#define IBMRGB_curs_hot_y 0x36 700#define IBMRGB_curs_col1_r 0x40 701#define IBMRGB_curs_col1_g 0x41 702#define IBMRGB_curs_col1_b 0x42 703#define IBMRGB_curs_col2_r 0x43 704#define IBMRGB_curs_col2_g 0x44 705#define IBMRGB_curs_col2_b 0x45 706#define IBMRGB_curs_col3_r 0x46 707#define IBMRGB_curs_col3_g 0x47 708#define IBMRGB_curs_col3_b 0x48 709#define IBMRGB_border_col_r 0x60 710#define IBMRGB_border_col_g 0x61 711#define IBMRGB_botder_col_b 0x62 712#define IBMRGB_misc1 0x70 713#define IBMRGB_misc2 0x71 714#define IBMRGB_misc3 0x72 715#define IBMRGB_misc4 0x73 /* not RGB525 */ 716#define IBMRGB_dac_sense 0x82 717#define IBMRGB_misr_r 0x84 718#define IBMRGB_misr_g 0x86 719#define IBMRGB_misr_b 0x88 720#define IBMRGB_pll_vco_div_in 0x8e 721#define IBMRGB_pll_ref_div_in 0x8f 722#define IBMRGB_vram_mask_0 0x90 723#define IBMRGB_vram_mask_1 0x91 724#define IBMRGB_vram_mask_2 0x92 725#define IBMRGB_vram_mask_3 0x93 726#define IBMRGB_curs_array 0x100 727 728#endif 729