Searched refs:DC_V_TIMING_1 (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Ddisp_gu1.c729 WRITE_REG32(DC_V_TIMING_1, value);
978 timing1 = READ_REG32(DC_V_TIMING_1);
987 WRITE_REG32(DC_V_TIMING_1,
2366 return ((unsigned short)((READ_REG32(DC_V_TIMING_1) & 0x07FF) + 1));
2397 return ((unsigned short)(((READ_REG32(DC_V_TIMING_1) >> 16) & 0x07FF) +
H A Dgfx_regs.h247 #define DC_V_TIMING_1 0x8340 /* vertical timing... */ macro
H A Dtv_fs450.c3256 #define DC_V_TIMING_1 0X8340
3350 (DC_V_TIMING_1 == inRegAddr) ||
3506 WriteGx(DC_V_TIMING_1, reg);
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Ddisp_gu1.c475 WRITE_REG32(DC_V_TIMING_1, value);
711 timing1 = READ_REG32(DC_V_TIMING_1);
718 WRITE_REG32(DC_V_TIMING_1,
2070 return ((unsigned short) ((READ_REG32(DC_V_TIMING_1) & 0x07FF) + 1));
2101 return ((unsigned short) (((READ_REG32(DC_V_TIMING_1) >> 16) & 0x07FF) +
H A Dgfx_regs.h146 #define DC_V_TIMING_1 0x8340 /* vertical timing... */ macro
H A Dtv_fs450.c3072 (DC_V_TIMING_1 == inRegAddr) ||
3228 WriteGx(DC_V_TIMING_1, reg);

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