Searched refs:DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_debug.c326 p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
1058 if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
H A Di830_display.c1642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2227 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
H A Di810_reg.h967 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_reg.h967 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_reg.h967 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro

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