Searched refs:DPLL_FPA01_P1_POST_DIV_MASK_IGD (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_reg.h972 # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_reg.h972 # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810_reg.h972 # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ macro
H A Di830_debug.c317 p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
H A Di830_display.c2219 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>

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