Searched refs:ET6000 (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/xf86-video-tseng/dist/src/
H A Dtseng_cursor.c49 if (pTseng->ChipType == ET6000) {
65 if (pTseng->ChipType == ET6000) {
100 if (pTseng->ChipType == ET6000) {
122 * The ET6000 cursor color is only 6 bits, with 2 bits per color. This
136 if (pTseng->ChipType == ET6000) {
186 if (pTseng->ChipType == ET6000) {
194 /* on the ET6000, bits (7:0) are always 0 */
H A Dtseng_accel.c19 * chips can do this. Only the ET6000 supports a transparency compare. The
20 * code could be easily changed to support transparency on the ET6000 and
166 if (pTseng->ChipType == ET6000) {
237 * ET6000 Yes No 8/16/24/32 bpp
240 if (pTseng->ChipType == ET6000) \
436 * This is for ET4000 only (The ET6000 cannot do this)
570 if ((pTseng->ChipType == ET6000) || (pScrn->bitsPerPixel == 8)) {
769 * planemask emulation uses a modified "standard" FG ROP (see ET6000
792 * Splitting it up between ET4000 and ET6000 avoids lots of chipset type
861 if ((pTseng->ChipType == ET6000)
[all...]
H A Dtseng.h53 ET6000 /* Both ET6000 and ET6100 */ enumerator in enum:__anoncd7dc6340103
57 * ET6000 and ET6100 have same pci id but differ by revision.
86 /* ET6000 PCI config space registers */
132 CARD32 ET6000IOAddress; /* PCI config space base address for ET6000 */
135 int MemClk; /* ET6000 only */
139 int max_vco_freq; /* ET6000: max internal VCO frequency */
H A Dtseng_driver.c24 * ET6000 and ET4000W32 16/24/32 bpp and acceleration support by Koen Gadeyne
123 {ET6000, "ET6000"},
134 {ET6000, PCI_CHIP_ET6000, RES_SHARED_VGA},
285 xf86Msg(X_INFO, TSENG_NAME ": driver for TsengLabs ET4000W32p, ET6000 and"
438 pTseng->ChipType = ET6000;
441 pScrn->chipset = "ET6000";
461 /* only the ET6000 implements a PCI IO address */
462 if (pTseng->ChipType == ET6000) {
471 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "ET6000 PC
[all...]
H A Dtseng_mode.c153 * ET6000 IO Range handling.
755 if (pTseng->ChipType == ET6000) {
809 if (pTseng->ChipType == ET6000) {
811 * According to Tseng (about the ET6000):
822 * current ET6000 chips. The ET6100 will raise the pixel clock limit
830 } else { /* ET6000 */
1112 /* Save ET6000 CLKDAC PLL registers */
1164 /* Restore ET6000 CLKDAC PLL registers */
1311 /* Don't ask me why this is needed on the ET6000 and not on the others */
1312 if (pTseng->ChipType == ET6000)
[all...]
H A Dtseng_accel.h12 /* for ET6000, ACL_SYNC_ENABLE becomes ACL_6K_CONFIG */
22 /* and this is only for the ET6000 */
25 /* non-queued for w32p's and ET6000 */
50 #define ACL_TRANSFER_DISABLE(x) MMIO_OUT8(pTseng->MMioBase, 0x91<<0, x) /* ET6000 only */
59 /* for ET6000, ACL_ROUTING_CONTROL becomes ACL_MIX_CONTROL */
61 /* for ET6000, ACL_RELOAD_CONTROL becomes ACL_STEPPING_INHIBIT */
77 /* ET6000 only (trapezoids) */
84 /* for ET6000: */
87 /* for ET6000: */
126 if (pTseng->ChipType == ET6000) \
[all...]

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