Searched refs:GFX7 (Results 1 - 25 of 70) sorted by relevance

123

/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_gfx_ver_enum.h32 GFX7 = (1 << 4), enumerator in enum:gfx_ver
55 case 70: return GFX7;
H A Dbrw_eu.cpp629 { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
630 { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
631 { BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
633 { BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
635 { BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
637 { BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
640 { BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
643 { BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
680 { BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
681 { BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dtest_tests.cpp56 for (int cls = GFX6; cls <= GFX7; cls++) {
H A Dtest_regalloc.cpp152 if (!setup_cs("v1 s1", GFX7))
170 if (!setup_cs("v2 s1", GFX7))
H A Dtest_to_hw_instr.cpp46 for (unsigned i = GFX6; i <= GFX7; i++) {
504 for (unsigned i = GFX7; i <= GFX9; i++) {
569 if (i != GFX7)
575 if (i != GFX7)
593 for (unsigned i = GFX7; i <= GFX9; i++) {
655 if (i != GFX7)
661 if (i != GFX7)
H A Dtest_isel.cpp62 for (unsigned i = GFX7; i <= GFX8; i++) {
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Damd_family.h87 CHIP_BONAIRE, /* GFX7 (Sea Islands) */
131 GFX7, enumerator in enum:chip_class
H A Dac_gpu_info.c260 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
644 info->chip_class = GFX7;
719 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
818 info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
847 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
849 info->has_clear_state = info->chip_class >= GFX7;
880 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
919 * Only GFX6 and certain GFX7 chips are affected.
1017 info->has_gds_ordered_append = info->chip_class >= GFX7 && info->drm_minor >= 29;
1469 if (info->chip_class >= GFX7) {
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c95 info->chip_class = GFX7;
128 info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c48 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
49 if (physical_device->rad_info.chip_class < GFX7)
60 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
61 if (physical_device->rad_info.chip_class < GFX7)
70 if (physical_device->rad_info.chip_class >= GFX7)
91 if (device->physical_device->rad_info.chip_class >= GFX7) {
174 if (physical_device->rad_info.chip_class >= GFX7)
221 if (physical_device->rad_info.chip_class < GFX7)
231 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
326 if (physical_device->rad_info.chip_class >= GFX7) {
[all...]
H A Dradv_sqtt.c181 device->physical_device->rad_info.chip_class >= GFX7) {
246 device->physical_device->rad_info.chip_class >= GFX7) {
376 family == RING_COMPUTE && device->physical_device->rad_info.chip_class >= GFX7,
H A Dradv_shader.h569 if (chip_class >= GFX7) {
607 if (chip_class >= GFX7 && family != CHIP_STONEY)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c260 /* HW limitation - GFX7: */
261 (sctx->chip_class != GFX7 ||
263 /* HW limitation - some GFX7 parts: */
281 if (sctx->chip_class == GFX7) {
405 if (sctx->chip_class == GFX7) {
425 if (sctx->screen->debug_flags & DBG(NO_DMA) || sctx->chip_class < GFX7)
451 case GFX7:
H A Dsi_state_draw.cpp36 #define GFX(name) name##GFX7
341 if (GFX_VERSION >= GFX7) {
413 if (GFX_VERSION < GFX7 || !mask)
693 if (sctx->chip_class >= GFX7) {
737 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
765 if (sctx->chip_class >= GFX7) {
831 if (sscreen->info.chip_class >= GFX7) {
864 /* Required on GFX7 and later. */
904 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
1019 if (GFX_VERSION == GFX7
[all...]
H A Dsi_cp_dma.c84 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
95 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
102 if (sctx->chip_class >= GFX7) {
397 assert(sctx->chip_class >= GFX7);
H A Dsi_fence.c80 if (ctx->chip_class >= GFX9 || (compute_ib && ctx->chip_class >= GFX7)) {
114 if (ctx->chip_class == GFX7 || ctx->chip_class == GFX8) {
152 if (screen->info.chip_class == GFX7 || screen->info.chip_class == GFX8)
H A Dsi_gpu_load.c104 if (sscreen->info.chip_class == GFX7 || sscreen->info.chip_class == GFX8) {
H A Dsi_pipe.c484 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
617 case GFX7:
673 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
675 if (sctx->chip_class == GFX7) {
767 if (sctx->chip_class == GFX7) {
1213 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1250 } else if (sscreen->info.chip_class >= GFX7) {
1264 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.3.rst135 - aco: fix emitting literal offsets with SMEM on GFX7
136 - radv: do not launch an IB2 for secondary cmdbuf with INDIRECT_MULTI on GFX7
H A D20.0.5.rst190 - radv/llvm: enable 8-bit storage features on GFX6-GFX7
193 - radv/llvm: enable 16-bit storage features on GFX6-GFX7
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c281 ws->info.chip_class = GFX7;
558 if (ws->info.chip_class == GFX7) {
583 /* HTILE is broken with 1D tiling on old kernels and GFX7. */
584 ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||
594 ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 ||
598 ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 &&
601 /* 2D tiling on GFX7 is supported since DRM 2.35.0 */
H A Dradeon_drm_surface.c60 if (info->chip_class >= GFX7)
307 if (info->chip_class >= GFX7 && num_pipes < 4)
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_assembler.cpp53 if (chip_class <= GFX7)
186 if (ctx.chip_class <= GFX7) {
202 /* SMRD instructions can take a literal on GFX7 */
387 assert(!mubuf.addr64 || ctx.chip_class <= GFX7);
388 if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7)
400 if (ctx.chip_class <= GFX7 || ctx.chip_class >= GFX10) {
611 if (ctx.chip_class <= GFX7) {
H A Daco_reduce_assign.cpp137 if (program->chip_class <= GFX7)
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_winsys.c61 ws->use_ib_bos = ws->info.chip_class >= GFX7;

Completed in 28 milliseconds

123