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    Searched refs:INREG8 (Results 1 - 25 of 35) sorted by relevancy

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  /xsrc/external/mit/xf86-video-i740/dist/src/
i740_macros.h 55 while (INREG8(LP_FIFO_COUNT) > 15-(n)); \
59 while (INREG8(HP_FIFO_COUNT) > 15-(n)); \
i740.h 53 #define INREG8(addr) *(volatile CARD8 *)(pI740->MMIOBase + (addr))
  /xsrc/external/mit/xf86-video-savage/dist/src/
savage_regs.h 227 byte = INREG8(CRT_DATA_REG) & 0X7F; \
246 INREG8(CRT_ADDRESS_REG); \
248 if (INREG8(CRT_DATA_REG) & 0x80) { \
250 while ((INREG8(SYSTEM_CONTROL_REG) & 0x08) == 0x08 && i--) ; \
252 while ((INREG8(SYSTEM_CONTROL_REG) & 0x08) == 0x00 && i--) ; \
265 OUTREG8(CRT_DATA_REG, INREG8(CRT_DATA_REG)); \
266 a = INREG8(CRT_DATA_REG); \
savage_accel.c 385 byte = INREG8(CRT_DATA_REG) | 0x80;
396 byte = INREG8(CRT_DATA_REG) | 0xC1;
474 byte = INREG8(CRT_DATA_REG) | DISABLE_BLOCK_WRITE_2D;
483 byte = INREG8(CRT_DATA_REG) & (~(ENABLE_CPUA_BASE_A0000));
488 byte = INREG8(SEQ_DATA_REG) & ~0x20;
547 byte = INREG8(CRT_DATA_REG) | 0x80;
558 byte = INREG8(CRT_DATA_REG) | 0xC1;
626 byte = INREG8(CRT_DATA_REG) | DISABLE_BLOCK_WRITE_2D;
635 byte = INREG8(CRT_DATA_REG) & (~(ENABLE_CPUA_BASE_A0000));
640 byte = INREG8(SEQ_DATA_REG) & ~0x20
    [all...]
savage_streams.c 425 OUTREG8(CRT_DATA_REG,INREG8(CRT_DATA_REG)|0x40);
429 OUTREG8(CRT_DATA_REG,INREG8(CRT_DATA_REG)|0x48);
435 OUTREG8(CRT_DATA_REG,(INREG8(CRT_DATA_REG)&0xf3)|0x04);
438 OUTREG8(CRT_DATA_REG,INREG8(CRT_DATA_REG)|0xC0);
  /xsrc/external/mit/xf86-video-mga/dist/src/
mga_macros.h 30 #define MGAISBUSY() (INREG8(MGAREG_Status + 2) & 0x01)
37 pMga->fifoCount = INREG8(MGAREG_FIFOSTATUS);\
mga_dacG.c 434 ucTempByte = INREG8(MGAREG_MEM_MISC_READ);
472 ucTempByte = INREG8(MGAREG_MEM_MISC_READ);
477 ucTempByte = INREG8(MGAREG_SEQ_DATA);
499 ucTempByte = INREG8(MGAREG_CRTCEXT_DATA);
516 ucTempByte = INREG8(MGAREG_MEM_MISC_READ);
566 ucTempByte = INREG8(MGAREG_SEQ_DATA);
695 ucTempByte = INREG8(MGAREG_MEM_MISC_READ);
774 ucTmpData = INREG8(MGAREG_CRTCEXT_DATA);
820 ucTempByte = INREG8(MGAREG_MEM_MISC_READ);
847 ucTempByte = INREG8(MGAREG_SEQ_DATA)
    [all...]
mga_g450pll.c 281 ucPLLStatus = INREG8(0x3c0a);
290 ucPLLStatus = INREG8(0x3c0a);
373 ucMisc = INREG8(0x1FCC);
mga.h 94 #define INREG8(addr) MMIO_IN8(pMga->IOBase, addr)
112 #define INREG8(addr) MGAdbg_inreg8(pScrn, addr, 1, __FUNCTION__)
162 #define inMGAdreg(reg) INREG8(RAMDAC_OFFSET + (reg))
200 status = INREG8( MGAREG_Status + 2 ); \
mga_dac3026.c 145 #define inTi3026dreg(reg) INREG8(RAMDAC_OFFSET + (reg))
836 mgaReg->ExtVga[i] = INREG8(0x1FDF);
889 while (INREG8(0x1FDA) & 0x01);
890 while (!(INREG8(0x1FDA) & 0x01));
mga_dh.c 251 ucByte = INREG8( MGAREG_MEM_MISC_READ);
  /xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
i810_cursor.c 222 tmp = INREG8(PIXPIPE_CONFIG_0);
233 tmp = INREG8(PIXPIPE_CONFIG_0);
252 tmp = INREG8(PIXPIPE_CONFIG_0);
267 tmp = INREG8(PIXPIPE_CONFIG_0);
i810_driver.c 713 ErrorF("instdone: %x instpm: %x\n", INREG16(INST_DONE), INREG8(INST_PM));
755 i810Reg->BitBLTControl = INREG8(BITBLT_CNTL);
758 i810Reg->VideoClk2_DivisorSel = INREG8(VCLK2_VCO_DIV_SEL);
769 i810Reg->PixelPipeCfg0 = INREG8(PIXPIPE_CONFIG_0);
770 i810Reg->PixelPipeCfg1 = INREG8(PIXPIPE_CONFIG_1);
771 i810Reg->PixelPipeCfg2 = INREG8(PIXPIPE_CONFIG_2);
772 i810Reg->DisplayControl = INREG8(DISPLAY_CNTL);
893 temp = INREG8(DRAM_ROW_CNTL_HI);
914 temp = INREG8(PIXPIPE_CONFIG_0);
974 temp = INREG8(DRAM_ROW_CNTL_HI)
    [all...]
i810_common.h 84 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
i810_cursor.c 222 tmp = INREG8(PIXPIPE_CONFIG_0);
233 tmp = INREG8(PIXPIPE_CONFIG_0);
252 tmp = INREG8(PIXPIPE_CONFIG_0);
267 tmp = INREG8(PIXPIPE_CONFIG_0);
i810_driver.c 713 ErrorF("instdone: %x instpm: %x\n", INREG16(INST_DONE), INREG8(INST_PM));
755 i810Reg->BitBLTControl = INREG8(BITBLT_CNTL);
758 i810Reg->VideoClk2_DivisorSel = INREG8(VCLK2_VCO_DIV_SEL);
769 i810Reg->PixelPipeCfg0 = INREG8(PIXPIPE_CONFIG_0);
770 i810Reg->PixelPipeCfg1 = INREG8(PIXPIPE_CONFIG_1);
771 i810Reg->PixelPipeCfg2 = INREG8(PIXPIPE_CONFIG_2);
772 i810Reg->DisplayControl = INREG8(DISPLAY_CNTL);
893 temp = INREG8(DRAM_ROW_CNTL_HI);
914 temp = INREG8(PIXPIPE_CONFIG_0);
974 temp = INREG8(DRAM_ROW_CNTL_HI)
    [all...]
i810_common.h 84 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i810_cursor.c 221 tmp = INREG8(PIXPIPE_CONFIG_0);
232 tmp = INREG8(PIXPIPE_CONFIG_0);
248 tmp = INREG8(PIXPIPE_CONFIG_0);
263 tmp = INREG8(PIXPIPE_CONFIG_0);
i810_driver.c 1060 ErrorF("instdone: %x instpm: %x\n", INREG16(INST_DONE), INREG8(INST_PM));
1102 i810Reg->BitBLTControl = INREG8(BITBLT_CNTL);
1105 i810Reg->VideoClk2_DivisorSel = INREG8(VCLK2_VCO_DIV_SEL);
1116 i810Reg->PixelPipeCfg0 = INREG8(PIXPIPE_CONFIG_0);
1117 i810Reg->PixelPipeCfg1 = INREG8(PIXPIPE_CONFIG_1);
1118 i810Reg->PixelPipeCfg2 = INREG8(PIXPIPE_CONFIG_2);
1119 i810Reg->DisplayControl = INREG8(DISPLAY_CNTL);
1240 temp = INREG8(DRAM_ROW_CNTL_HI);
1261 temp = INREG8(PIXPIPE_CONFIG_0);
1321 temp = INREG8(DRAM_ROW_CNTL_HI)
    [all...]
i830_debug.c 1485 name, i, INREG8(val));
1496 msr = INREG8(0x3cc);
1502 INREG8(st01); /* make sure index/write register is in index mode */
1503 orig_arx = INREG8(0x3c0);
1508 INREG8(st01);
1511 "AR", i, INREG8(0x3c1));
1513 INREG8(st01);
1515 INREG8(st01); /* switch back to index mode */
1583 msr = INREG8(0x3cc);
2341 INREG16(INST_DONE), INREG8(INST_PM))
    [all...]
common.h 117 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
  /xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/
reg_dumper.h 70 #define INREG8(reg) (*(volatile uint8_t *)((pI830)->mmio + (reg)))
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_mm_i2c.c 34 reg = INREG8(RADEON_I2C_CNTL_0+1); \
78 retval = INREG8(RADEON_I2C_CNTL_0);
110 reg = INREG8 (RADEON_I2C_CNTL_0 + 0) & ~(RADEON_I2C_DONE|RADEON_I2C_NACK|RADEON_I2C_HALT);
115 reg = INREG8 (RADEON_I2C_CNTL_0 + 1) & 0xE7;
196 ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
280 ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
radeon_macros.h 63 #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
  /xsrc/external/mit/xf86-video-neomagic/dist/src/
neo.h 300 #define INREG8(addr) MMIO_IN8(nPtr->NeoMMIOBase, addr)

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