1 2#ifndef SAVAGE_REGS_H 3#define SAVAGE_REGS_H 4 5/* Copied and renamed from radeon_reg.h for AGP/PCI detection. */ 6#define SAVAGE_STATUS_PCI_CONFIG 0x06 7# define SAVAGE_CAP_LIST 0x100000 8#define SAVAGE_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ 9# define SAVAGE_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ 10# define SAVAGE_CAP_ID_NULL 0x00 /* End of capability list */ 11# define SAVAGE_CAP_ID_AGP 0x02 /* AGP capability ID */ 12 13#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 14 15#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 16 || (chip==S3_PROSAVAGE) \ 17 || (chip==S3_TWISTER) \ 18 || (chip==S3_PROSAVAGEDDR)) 19 20#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 21 22#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 23 24#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 25 ||(chip==S3_PROSAVAGEDDR)) 26 27/* Chip tags. These are used to group the adapters into 28 * related families. 29 */ 30 31enum S3CHIPTAGS { 32 S3_UNKNOWN = 0, 33 S3_SAVAGE3D, 34 S3_SAVAGE_MX, 35 S3_SAVAGE4, 36 S3_PROSAVAGE, 37 S3_TWISTER, 38 S3_PROSAVAGEDDR, 39 S3_SUPERSAVAGE, 40 S3_SAVAGE2000, 41 S3_LAST 42}; 43 44#define BIOS_BSIZE 1024 45#define BIOS_BASE 0xc0000 46 47#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ 48#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 49#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ 50#define SAVAGE_NEWMMIO_VGABASE 0x8000 51 52#define BASE_FREQ 14.31818 53 54#define FIFO_CONTROL_REG 0x8200 55#define MIU_CONTROL_REG 0x8204 56#define STREAMS_TIMEOUT_REG 0x8208 57#define MISC_TIMEOUT_REG 0x820c 58 59#define ADVANCED_FUNC_CTRL 0x850C 60 61/* 62 * CR/SR registers MMIO offset 63 * MISC Output Register(W:0x3c2,R:0x3cc) controls CR is 0X83Cx or 0X83Bx 64 * but do we need to set MISC Output Register ??? 65 * (Note that CRT_ADDRESS_REG and CRT_DATA_REG are assumed to be COLOR)??? 66 */ 67#define MMIO_BASE_OF_VGA3C0 0X83C0 68#define MMIO_BASE_OF_VGA3D0 0X83D0 69 70#define ATTR_ADDRESS_REG \ 71 (MMIO_BASE_OF_VGA3C0 + (0x03C0 - 0x03C0)) 72#define ATTR_DATA_WRITE_REG \ 73 (MMIO_BASE_OF_VGA3C0 + (0x03C0 - 0x03C0)) 74#define ATTR_DATA_READ_REG \ 75 (MMIO_BASE_OF_VGA3C0 + (0x03C1 - 0x03C0)) 76#define VIDEO_SUBSYSTEM_ENABLE \ 77 (MMIO_BASE_OF_VGA3C0 + (0x03C3 - 0x03C0)) 78#define SEQ_ADDRESS_REG \ 79 (MMIO_BASE_OF_VGA3C0 + (0x03C4 - 0x03C0)) 80#define SEQ_DATA_REG \ 81 (MMIO_BASE_OF_VGA3C0 + (0x03C5 - 0x03C0)) 82#define DAC_PIXEL_MASK_REG \ 83 (MMIO_BASE_OF_VGA3C0 + (0x03C6 - 0x03C0)) 84#define DAC_PEL_MASK \ 85 (MMIO_BASE_OF_VGA3C0 + (0x03C6 - 0x03C0)) 86#define DAC_STATUS_REG \ 87 (MMIO_BASE_OF_VGA3C0 + (0x03C7 - 0x03C0)) 88#define DAC_ADDRESS_READ_REG \ 89 (MMIO_BASE_OF_VGA3C0 + (0x03C7 - 0x03C0)) 90#define DAC_ADDRESS_WRITE_REG \ 91 (MMIO_BASE_OF_VGA3C0 + (0x03C8 - 0x03C0)) 92#define DAC_DATA_REG \ 93 (MMIO_BASE_OF_VGA3C0 + (0x03C9 - 0x03C0)) 94#define DAC_DATA_REG_PORT \ 95 (MMIO_BASE_OF_VGA3C0 + (0x03C9 - 0x03C0)) 96#define MISC_OUTPUT_REG_WRITE \ 97 (MMIO_BASE_OF_VGA3C0 + (0x03C2 - 0x03C0)) 98#define MISC_OUTPUT_REG_READ \ 99 (MMIO_BASE_OF_VGA3C0 + (0x03CC - 0x03C0)) 100#define GR_ADDRESS_REG \ 101 (MMIO_BASE_OF_VGA3C0 + (0x03CE - 0x03C0)) 102#define GR_DATA_REG \ 103 (MMIO_BASE_OF_VGA3C0 + (0x03CF - 0x03C0)) 104#define WAKEUP_REG \ 105 (MMIO_BASE_OF_VGA3C0 + (0x0510 - 0x03C0)) 106 107#define CRT_ADDRESS_REG \ 108 (MMIO_BASE_OF_VGA3D0 + (0x03D4 - 0x03D0)) 109#define CRT_DATA_REG \ 110 (MMIO_BASE_OF_VGA3D0 + (0x03D5 - 0x03D0)) 111#define SYSTEM_CONTROL_REG \ 112 (MMIO_BASE_OF_VGA3D0 + (0x03DA - 0x03D0)) 113 114/* GX-3 Configuration/Status Registers */ 115#define S3_SHADOW_STATUS 0x48C0C 116#define S3_BUFFER_THRESHOLD 0x48C10 117#define S3_OVERFLOW_BUFFER 0x48C14 118#define S3_OVERFLOW_BUFFER_PTR 0x48C18 119 120#define ENABLE_BCI 0x08 /* MM48C18_3 */ 121#define ENABLE_COMMAND_OVERFLOW_BUF 0x04 /* MM48C18_2 */ 122#define ENABLE_COMMAND_BUF_STATUS_UPDATE 0x02 /* MM48C18_1 */ 123#define ENABLE_SHADOW_STATUS_UPDATE 0x01 /* MM48C0C_0 */ 124 125 126#define MEMORY_CTRL0_REG 0xCA 127#define MEMORY_CTRL1_REG 0xCB 128#define MEMORY_CTRL2_REG 0xCC 129 130#define MEMORY_CONFIG_REG 0x31 131 132/* bitmap descriptor register */ 133#define S3_GLB_BD_LOW 0X8168 134#define S3_GLB_BD_HIGH 0X816C 135#define S3_PRI_BD_LOW 0X8170 136#define S3_PRI_BD_HIGH 0X8174 137#define S3_SEC_BD_LOW 0X8178 138#define S3_SEC_BD_HIGH 0X817c 139 140/* duoview */ 141 142#define SELECT_IGA1 0x4026 143#define SELECT_IGA2_READS_WRITES 0x4f26 144 145#define SelectIGA1() \ 146do { \ 147 OUTREG16(SEQ_ADDRESS_REG,SELECT_IGA1); \ 148} while (0) 149 150#define SelectIGA2() \ 151do { \ 152 OUTREG16(SEQ_ADDRESS_REG,SELECT_IGA2_READS_WRITES); \ 153} while (0) 154 155#define MEM_PS1 0x10 /*CRCA_4 :Primary stream 1*/ 156#define MEM_PS2 0x20 /*CRCA_5 :Primary stream 2*/ 157#define MEM_SS1 0x40 /*CRCA_6 :Secondary stream 1*/ 158#define MEM_SS2 0x80 /*CRCA_7 :Secondary stream 2*/ 159 160#define SUBSYS_STAT_REG 0x8504 161 162#define SRC_BASE 0xa4d4 163#define DEST_BASE 0xa4d8 164#define CLIP_L_R 0xa4dc 165#define CLIP_T_B 0xa4e0 166#define DEST_SRC_STR 0xa4e4 167#define MONO_PAT_0 0xa4e8 168#define MONO_PAT_1 0xa4ec 169 170#define TILED_SURFACE_REGISTER_0 0x48c40 171#define TILED_SURFACE_REGISTER_1 0x48c44 172#define TILED_SURFACE_REGISTER_2 0x48c48 173#define TILED_SURFACE_REGISTER_3 0x48c4c 174#define TILED_SURFACE_REGISTER_4 0x48c50 175 176#define TILED_SURF_BPP4 0x00000000 /* bits 31-30=00 for 4 bits/pixel */ 177#define TILED_SURF_BPP8 0x40000000 /* bits 31-30=01 for 8 bits/pixel */ 178#define TILED_SURF_BPP16 0x80000000 /* bits 31-30=10 for 16 bits/pixel */ 179#define TILED_SURF_BPP32 0xC0000000 /* bits 31-30=11 for 32 bits/pixel */ 180 181#define TILED_SURF_BPP16_2000 0x00000000 /* bit 31=0 for 16 bits/pixel */ 182#define TILED_SURF_BPP32_2000 0x80000000 /* bit 31=1 for 32 bits/pixel */ 183 184/* 185 * CR88_4 =1 : disable block write 186 * the "2D" is partly to set this apart from "BLOCK_WRITE_DISABLE" 187 * constant used for bitmap descriptor 188 */ 189#define DISABLE_BLOCK_WRITE_2D 0x10 190#define BLOCK_WRITE_DISABLE 0x0 191 192/* CR31[0] set = Enable 8MB display memory through 64K window at A0000H. */ 193#define ENABLE_CPUA_BASE_A0000 0x01 194 195/* Constants for CR69. */ 196 197#define CRT_ACTIVE 0x01 198#define LCD_ACTIVE 0x02 199#define TV_ACTIVE 0x04 200#define CRT_ATTACHED 0x10 201#define LCD_ATTACHED 0x20 202#define TV_ATTACHED 0x40 203 204 205/* 206 * reads from SUBSYS_STAT 207 */ 208#define STATUS_WORD0 (INREG(0x48C00)) 209#define ALT_STATUS_WORD0 (INREG(0x48C60)) 210#define MAXLOOP 0xffffff 211#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) 212 213#define MAXFIFO 0x7f00 214 215#define inStatus1() (VGAHWPTR(pScrn))->readST01( VGAHWPTR(pScrn) ) 216 217 218/* 219 * unprotect CRTC[0-7] 220 * CR11_7 = 0: Writing to all CRT Controller registers enabled 221 * = 1: Writing to all bits of CR0~CR7 except CR7_4 disabled 222 */ 223#define UnProtectCRTC() \ 224do { \ 225 unsigned char byte; \ 226 OUTREG8(CRT_ADDRESS_REG,0x11); \ 227 byte = INREG8(CRT_DATA_REG) & 0X7F; \ 228 OUTREG16(CRT_ADDRESS_REG,byte << 8 | 0x11); \ 229} while (0) 230 231/* 232 * unlock extended regs 233 * CR38:unlock CR20~CR3F 234 * CR39:unlock CR40~CRFF 235 * SR08:unlock SR09~SRFF 236 */ 237#define UnLockExtRegs() \ 238do { \ 239 OUTREG16(CRT_ADDRESS_REG,0X4838); \ 240 OUTREG16(CRT_ADDRESS_REG,0XA039); \ 241 OUTREG16(SEQ_ADDRESS_REG,0X0608); \ 242} while (0) 243 244#define VerticalRetraceWait() \ 245do { \ 246 INREG8(CRT_ADDRESS_REG); \ 247 OUTREG8(CRT_ADDRESS_REG, 0x17); \ 248 if (INREG8(CRT_DATA_REG) & 0x80) { \ 249 int i = 0x10000; \ 250 while ((INREG8(SYSTEM_CONTROL_REG) & 0x08) == 0x08 && i--) ; \ 251 i = 0x10000; \ 252 while ((INREG8(SYSTEM_CONTROL_REG) & 0x08) == 0x00 && i--) ; \ 253 } \ 254} while (0) 255 256/* 257 * Jiayo Hsu, Mar 21, 2002 258 * modify this to scalable schema, because different chips have different regs, 259 * besides add in patch code for Paramount(SuperSavage) from 2K 260 */ 261#define InI2CREG(a,reg) \ 262do { \ 263 OUTREG8(CRT_ADDRESS_REG, reg); \ 264 if (psav->Chipset == S3_SUPERSAVAGE) \ 265 OUTREG8(CRT_DATA_REG, INREG8(CRT_DATA_REG)); \ 266 a = INREG8(CRT_DATA_REG); \ 267} while (0) 268 269#define OutI2CREG(a,reg) \ 270do { \ 271 OUTREG8(CRT_ADDRESS_REG, reg); \ 272 if (psav->Chipset == S3_SUPERSAVAGE) \ 273 OUTREG8(CRT_DATA_REG, a); \ 274 OUTREG8(CRT_DATA_REG, a); \ 275} while (0) 276 277#define HZEXP_COMP_1 0x54 278#define HZEXP_BORDER 0x58 279#define HZEXP_FACTOR_IGA1 0x59 280 281#define VTEXP_COMP_1 0x56 282#define VTEXP_BORDER 0x5a 283#define VTEXP_FACTOR_IGA1 0x5b 284 285#define EC1_CENTER_ON 0x10 286#define EC1_EXPAND_ON 0x0c 287 288#endif /* SAVAGE_REGS_H */ 289