Searched refs:IR3_DBG_RAMSGS (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_compiler.h204 IR3_DBG_RAMSGS = BITFIELD_BIT(21), enumerator in enum:ir3_shader_debug
H A Dir3_compiler.c51 {"ramsgs", IR3_DBG_RAMSGS, "Enable register-allocation debug messages"},
H A Dir3_ra.h32 #define RA_DEBUG (ir3_shader_debug & IR3_DBG_RAMSGS)
H A Dir3_merge_regs.c580 if (ir3_shader_debug & IR3_DBG_RAMSGS)

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