Searched refs:L0 (Results 1 - 4 of 4) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/main/ |
| H A D | texcompress_astc.cpp | 1008 int s0, s1, L0, L1; local in function:Block::decode_colour_endpoints
1017 L0 = (v0 >> 2) | (v1 & 0xc0);
1018 L1 = L0 + (v1 & 0x3f);
1021 e0 = uint8x4_t(L0, L0, L0, 0xff);
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README-ISA.md | 126 ## RDNA L0, L1 cache and DLC, GLC bits
128 The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The
133 * GLC ("globally coherent") bit: controls the L0 cache
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| /xsrc/external/mit/MesaLib/dist/src/mesa/main/ |
| H A D | texcompress_astc.cpp | 1009 int s0, s1, L0, L1; local in function:Block::decode_colour_endpoints
1018 L0 = (v0 >> 2) | (v1 & 0xc0);
1019 L1 = L0 + (v1 & 0x3f);
1022 e0 = uint8x4_t(L0, L0, L0, 0xff);
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.2.0.rst | 3229 - ac/nir: honor ACCESS_STREAM_CACHE_POLICY for L1 and L0 caches too
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