Searched refs:MASK (Results 1 - 25 of 67) sorted by relevance

123

/xsrc/external/mit/libX11/dist/src/xcms/
H A DXRGB.c47 static unsigned short const MASK[17] = { variable in typeref:typename:unsigned short const[17]
136 pColors->spec.RGB.red = (pXColors->red & MASK[bits_per_rgb]);
137 pColors->spec.RGB.green = (pXColors->green & MASK[bits_per_rgb]);
138 pColors->spec.RGB.blue = (pXColors->blue & MASK[bits_per_rgb]);
216 pColor->spec.RGB.red &= MASK[bits_per_rgb];
217 pColor->spec.RGB.green &= MASK[bits_per_rgb];
218 pColor->spec.RGB.blue &= MASK[bits_per_rgb];
243 pXColor->red &= MASK[bits_per_rgb];
244 pXColor->green &= MASK[bits_per_rgb];
245 pXColor->blue &= MASK[bits_per_rg
[all...]
/xsrc/external/mit/pixman/dist/pixman/
H A Dpixman-arm-simd-asm.S68 WK6 .req MASK
121 mov MASK, SRC
129 mov MASK, SRC
138 mov MASK, SRC
145 WK6 .req MASK
218 /* Hold loop invariants in MASK and STRIDE_M */
219 ldr MASK, =0x07E007E0
227 and SCRATCH, WK\()\reg1, MASK @ 00000GGGGGG0000000000gggggg00000
228 bic WK\()\reg2, WK\()\reg1, MASK @ RRRRR000000BBBBBrrrrr000000bbbbb
246 and SCRATCH, WK\()\reg1, MASK
[all...]
H A Dpixman-combine32.h2 #define MASK 0xff macro
18 #define RED_8(x) (((x) >> R_SHIFT) & MASK)
19 #define GREEN_8(x) (((x) >> G_SHIFT) & MASK)
20 #define BLUE_8(x) ((x) & MASK)
71 (((uint16_t) (a) * MASK + ((b) / 2)) / (b))
118 t = (x & MASK) * (a & MASK); \
119 t |= (x & R_MASK) * ((a >> R_SHIFT) & MASK); \
H A Dpixman-arm-neon-asm.h445 pld [MASK, #(PREFETCH_DISTANCE_SIMPLE * mask_bpp / 8)]
452 (mask_basereg - pixblock_size * mask_bpp / 64), MASK
474 pixld (\lowbit * 8 / dst_w_bpp), mask_bpp, mask_basereg, MASK
536 pixld \chunk_size, mask_bpp, mask_basereg, MASK
590 add MASK, MASK, MASK_STRIDE, lsl #mask_bpp_shift
599 sub MASK, MASK, W, lsl #mask_bpp_shift
681 MASK .req r7 /* mask pointer */
776 ldr MASK, [s
[all...]
H A Dpixman-arm-simd-asm.h289 * "base" - base address register of channel to preload (SRC, MASK or DST)
445 preload_middle mask_bpp, MASK, 1
448 preload_middle mask_bpp, MASK, 0
484 preload_trailing mask_bpp, mask_bpp_shift, MASK
519 tst MASK, #3
566 add MASK, MASK, STRIDE_M
702 MASK .req r6 /* mask pixel pointer (if applicable) */
725 ldr MASK, [sp, #ARGS_STACK_OFFSET+8]
778 preload_leading_step1 mask_bpp, WK2, MASK
[all...]
H A Dpixman-arma64-neon-asm.h506 prfm PREFETCH_MODE, [MASK, #(PREFETCH_DISTANCE_SIMPLE * mask_bpp / 8)]
513 (mask_basereg - pixblock_size * mask_bpp / 64), MASK
537 pixld (\lowbit * 8 / dst_w_bpp), mask_bpp, mask_basereg, MASK
605 pixld \chunk_size, mask_bpp, mask_basereg, MASK
656 add MASK, MASK, MASK_STRIDE, lsl #mask_bpp_shift
665 sub MASK, MASK, W, lsl #mask_bpp_shift
757 MASK .req x6 /* mask pointer */
855 PF mov, PF_MASK, MASK
[all...]
H A Dpixman-arm-neon-asm-bilinear.S45 * Assume that symbol(register .req) OUT and MASK are defined at caller of these macro blocks.
228 vld1.32 {\mask[0]}, [MASK]!
230 vld1.16 {\mask[0]}, [MASK]!
232 vld1.8 {\mask[0]}, [MASK]!
236 pld [MASK, #prefetch_offset]
644 MASK .req r1
768 .unreq MASK
1096 vld1.32 {d22[0]}, [MASK]!
1097 pld [MASK, #prefetch_offset]
1214 vld1.32 {d22[0]}, [MASK]!
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_lower_spill.c51 spill->srcs[1]->wrmask = MASK(orig_components);
63 clone->srcs[1]->wrmask = MASK(components);
86 reload->dsts[0]->wrmask = MASK(orig_components);
98 clone->dsts[0]->wrmask = MASK(components);
H A Dir3_a6xx.c52 ldib->dsts[0]->wrmask = MASK(intr->num_components);
211 ldib->dsts[0]->wrmask = MASK(intr->num_components);
360 resinfo->dsts[0]->wrmask = MASK(3);
385 load->dsts[0]->wrmask = MASK(dest_components);
H A Dir3_a4xx.c55 ldgb->dsts[0]->wrmask = MASK(intr->num_components);
246 ldib->dsts[0]->wrmask = MASK(intr->num_components);
/xsrc/external/mit/xf86-video-xgi/dist/src/
H A Dvb_i2c.h81 //#define MASK(n) BITSMASK(1?n, 0?n)
83 #define MASK(n) ( BITS(LARGE(n)-SMALL(n)+1) << SMALL(n) ) macro
87 #define GETBITS(b,n) ( ((b) & MASK(n)) >> SMALL(n) ) /* Jong@08032009 */
90 #define SETBITS(b, n) ( ( (b) << ((1?n) > (0?n) ? (0?n) : (1?n)) ) & MASK(n) )
H A Dvb_i2c.c1197 pHWDE->ucI2cDVI = (pHWDE->ucI2cDVI & MASK(1:1)) | SETBITS(data, 0:0);
1209 temp = (temp & (~MASK(1:0))) | pHWDE->ucI2cDVI;
1248 pHWDE->ucI2cDVI = (pHWDE->ucI2cDVI & MASK(0:0)) | SETBITS(data, 1:1);
1261 temp = (temp & (~MASK(1:0))) | pHWDE->ucI2cDVI;
1408 pHWDE->ucI2cCRT = (pHWDE->ucI2cCRT & MASK(1:1)) | SETBITS(data, 0:0);
1411 temp = (temp & (~MASK(1:0))) | pHWDE->ucI2cCRT;
1443 pHWDE->ucI2cCRT = (pHWDE->ucI2cCRT & MASK(0:0)) | SETBITS(data, 1:1);
1445 temp = (temp & (~MASK(1:0))) | pHWDE->ucI2cCRT;
1525 pHWDE->ucI2cFCNT = (pHWDE->ucI2cFCNT & MASK(3:3)) | SETBITS(data, 2:2);
1528 temp = (temp & (~MASK(
[all...]
H A Dvb_struct.h206 USHORT MASK; member in struct:_XGI_LCDDataTablStruct
213 USHORT MASK; member in struct:_XGI_TVTablDataStruct
272 USHORT MASK; member in struct:_XGI330_LCDDataTablStruct
279 USHORT MASK; member in struct:_XGI330_TVDataTablStruct
/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/valhall/
H A Ddisassemble.h13 #define MASK(count) ((1ull << (count)) - 1) macro
/xsrc/external/mit/xf86-video-i128/dist/src/
H A Di128accel.c201 pI128->mem.rbase_a[MASK] = -1;
204 pI128->mem.rbase_a[MASK] = planemask |
210 pI128->mem.rbase_a[MASK] = planemask | (planemask<<16);
215 pI128->mem.rbase_a[MASK] = planemask;
262 pI128->mem.rbase_a[MASK] = -1;
265 pI128->mem.rbase_a[MASK] = planemask |
271 pI128->mem.rbase_a[MASK] = planemask | (planemask<<16);
276 pI128->mem.rbase_a[MASK] = planemask;
373 pI128->mem.rbase_a[MASK] = planemask;
/xsrc/external/mit/xkill/dist/
H A Dxkill.c269 #define MASK (ButtonPressMask | ButtonReleaseMask) macro
287 if (XGrabPointer (dpy, root, False, MASK, GrabModeSync, GrabModeAsync,
298 XWindowEvent (dpy, root, MASK, &event);
/xsrc/external/mit/MesaLib/dist/src/asahi/compiler/
H A Dagx_opcodes.py87 MASK = immediate("mask") variable
198 srcs = 5, imms = [DIM, LOD_MODE, MASK, SCOREBOARD])
203 srcs = 2, imms = [FORMAT, MASK, SCOREBOARD])
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/tests/
H A Ddelay.c130 instr->dsts[0]->wrmask = MASK(instr->repeat + 1);
136 reg->wrmask = MASK(instr->repeat + 1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_image.c90 img->width = sz & MASK(15);
163 img->width = sz & MASK(15);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/
H A Dbackend_impl.h52 #define MASK 0xff macro
196 uint32_t centerCoverage = ((uint32_t)(*coverageMask) & MASK);
413 uint32_t simdCoverage = (coverageMask[0] & MASK);
730 _simd_and_ps(activeLanes, _simd_vmask_ps(pCoverageMask[currentSimdIn8x8] & MASK));
1062 if (!(work.anyCoveredSamples & MASK))
1066 activeLanes = _simd_vmask_ps(work.anyCoveredSamples & MASK);
/xsrc/external/mit/xf86-video-intel/dist/test/
H A Drender-glyphs.c64 GLYPHS, OP, DST, SRC, MASK, CLIP, enumerator in enum:glyph_iter::__anon8bf282650103
255 if (gi->stage == MASK) {
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_image.c92 img->width = sz & MASK(15);
171 img->width = sz & MASK(15);
/xsrc/external/mit/brotli/dist/c/enc/
H A Dhash.h333 #define MASK ((NUMBUCKETS * 64) - 1) macro
342 #undef MASK
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dbuilder_misc.h117 Value* MASK(Value* vmask);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_image.c93 img->width = sz & MASK(15);

Completed in 32 milliseconds

123