Searched refs:MAX_XFB_BUFFERS (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c2656 for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
3319 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3320 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3321 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
3332 for (uint32_t idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
3372 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
3373 assert(counterBufferCount <= MAX_XFB_BUFFERS);
3374 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
H A DgenX_pipeline.c1193 int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0};
1251 for (unsigned b = 0; b < MAX_XFB_BUFFERS; b++) {
H A Danv_cmd_buffer.c640 assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
H A Danv_private.h153 #define MAX_XFB_BUFFERS 4 macro
2357 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
H A Danv_device.c1577 props->maxTransformFeedbackBuffers = MAX_XFB_BUFFERS;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c3650 for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
4623 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
4624 assert(counterBufferCount <= MAX_XFB_BUFFERS);
4625 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
4638 for (uint32_t idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
4678 assert(firstCounterBuffer < MAX_XFB_BUFFERS);
4679 assert(counterBufferCount <= MAX_XFB_BUFFERS);
4680 assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
H A DgenX_pipeline.c1611 int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0};
1685 for (unsigned b = 0; b < MAX_XFB_BUFFERS; b++) {
H A Danv_cmd_buffer.c1085 assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
H A Danv_private.h183 #define MAX_XFB_BUFFERS 4 macro
3002 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
H A Danv_device.c2463 props->maxTransformFeedbackBuffers = MAX_XFB_BUFFERS;

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