Searched refs:MESA_SHADER_CALLABLE (Results 1 - 13 of 13) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_nir_lower_shader_calls.c76 case MESA_SHADER_CALLABLE:
261 compiler->glsl_compiler_options[MESA_SHADER_CALLABLE].NirOptions;
263 nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE,
H A Dbrw_compiler.c253 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
275 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
H A Dbrw_nir_rt.c382 assert(nir->info.stage == MESA_SHADER_CALLABLE);
H A Dbrw_compiler.h147 stage <= MESA_SHADER_CALLABLE;
H A Dbrw_fs_nir.cpp451 case MESA_SHADER_CALLABLE:
H A Dbrw_fs.cpp9368 assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
/xsrc/external/mit/MesaLib/dist/src/compiler/
H A Dshader_enums.c53 ENUM(MESA_SHADER_CALLABLE),
82 case MESA_SHADER_CALLABLE: return "callable";
110 case MESA_SHADER_CALLABLE: return "RCALL";
H A Dshader_enums.h63 MESA_SHADER_CALLABLE = 13, enumerator in enum:__anon671c309a0103
91 stage == MESA_SHADER_CALLABLE;
124 #define MESA_VULKAN_SHADER_STAGES (MESA_SHADER_CALLABLE + 1)
/xsrc/external/mit/MesaLib/dist/src/intel/dev/
H A Dintel_debug.c120 [MESA_SHADER_CALLABLE] = DEBUG_RT,
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_pipeline.c2640 2 * stack_max[MESA_SHADER_CALLABLE];
2869 case MESA_SHADER_CALLABLE:
3073 MESA_SHADER_CALLABLE,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_program.c93 case MESA_SHADER_CALLABLE:
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline_rt.c851 return MESA_SHADER_CALLABLE;
869 shader->info.stage == MESA_SHADER_CALLABLE || shader->info.stage == MESA_SHADER_MISS) {
/xsrc/external/mit/MesaLib/dist/src/compiler/spirv/
H A Dspirv_to_nir.c4297 return MESA_SHADER_CALLABLE;

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