Searched refs:NOPs (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_insert_NOPs.cpp271 handle_raw_hazard(State& state, int* NOPs, int min_states, Operand op) argument
273 if (*NOPs >= min_states)
277 *NOPs = MAX2(*NOPs, res);
325 int* NOPs)
328 if (!*NOPs & (ctx.smem_clause || ctx.smem_write)) {
333 *NOPs = 1;
338 *NOPs = 1;
344 if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size()))
345 *NOPs
324 handle_smem_clause_hazards(Program * program,NOP_ctx_gfx6 & ctx,aco_ptr<Instruction> & instr,int * NOPs) argument
356 int NOPs = 0; local in function:aco::__anonc617705e0110::handle_instruction_gfx6
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H A DREADME-ISA.md85 also seems unlikely, since NOPs are apparently needed in a subset of these
229 Any branch that is located at offset 0x3f will be buggy. Just insert some NOPs to make sure no branch
H A DREADME.md105 #### Resolve hazards and insert NOPs
/xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/
H A Dir3-notes.rst6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.1.0.rst3249 - intel/compiler: Discount NOPs from instruction counts
H A D21.0.0.rst1091 - freedreno/ir3: Include at least 4 NOPs so that cffdump doesn't disasm junk.
H A D21.1.0.rst2068 - docs: nops -> NOPs

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