Searched refs:OUT_CB_REG (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/
H A Dr300_context.c292 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
295 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
302 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
309 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
315 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
318 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
323 OUT_CB_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
334 OUT_CB_REG(R300_GB_SELECT, 0);
335 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
336 OUT_CB_REG(R300_GA_OFFSE
[all...]
H A Dr300_fs.c259 OUT_CB_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
260 OUT_CB_REG(R500_US_PIXSIZE, code->max_temp_idx);
261 OUT_CB_REG(R500_US_FC_CTRL, code->us_fc_ctrl);
263 OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
266 OUT_CB_REG(R500_US_CODE_RANGE,
268 OUT_CB_REG(R500_US_CODE_OFFSET, 0);
269 OUT_CB_REG(R500_US_CODE_ADDR,
272 OUT_CB_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
289 OUT_CB_REG(R500_GA_US_VECTOR_INDEX,
325 OUT_CB_REG(R300_US_CONFI
[all...]
H A Dr300_cb.h130 #define OUT_CB_REG(register, value) do { \ macro
H A Dr300_state.c487 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
492 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
499 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
504 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
509 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
514 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
519 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
524 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
648 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui[0]);
665 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_RE
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/
H A Dr300_context.c291 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
294 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
301 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
308 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
314 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
317 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
322 OUT_CB_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
333 OUT_CB_REG(R300_GB_SELECT, 0);
334 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
335 OUT_CB_REG(R300_GA_OFFSE
[all...]
H A Dr300_fs.c259 OUT_CB_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
260 OUT_CB_REG(R500_US_PIXSIZE, code->max_temp_idx);
261 OUT_CB_REG(R500_US_FC_CTRL, code->us_fc_ctrl);
263 OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
266 OUT_CB_REG(R500_US_CODE_RANGE,
268 OUT_CB_REG(R500_US_CODE_OFFSET, 0);
269 OUT_CB_REG(R500_US_CODE_ADDR,
272 OUT_CB_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
289 OUT_CB_REG(R500_GA_US_VECTOR_INDEX,
325 OUT_CB_REG(R300_US_CONFI
[all...]
H A Dr300_cb.h130 #define OUT_CB_REG(register, value) do { \ macro
H A Dr300_state.c481 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
486 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
493 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
498 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
503 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
508 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
513 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
518 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
642 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui[0]);
659 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_RE
[all...]

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