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    Searched refs:OUT_RING_REG (Results 1 - 13 of 13) sorted by relevancy

  /xsrc/external/mit/xf86-video-ati-kms/dist/src/
radeon_accel.c 227 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
228 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
229 OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
233 OUT_RING_REG(R300_GB_AA_CONFIG, 0);
234 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
235 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
239 OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
240 OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
242 OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
250 OUT_RING_REG(R300_GA_OFFSET, 0)
    [all...]
radeon_textured_videofuncs.c 119 OUT_RING_REG(RADEON_RB3D_CNTL, dst_format);
122 OUT_RING_REG(RADEON_RB3D_BLENDCNTL,
140 OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
144 OUT_RING_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
150 OUT_RING_REG(RADEON_PP_TXFILTER_0,
156 OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
158 OUT_RING_REG(RADEON_PP_TXCBLEND_0,
164 OUT_RING_REG(RADEON_PP_TXABLEND_0,
171 OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
174 OUT_RING_REG(RADEON_PP_TEX_PITCH_0
    [all...]
radeon_exa_render.c 432 OUT_RING_REG(RADEON_PP_TXFILTER_0, txfilter);
433 OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat);
434 OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
437 OUT_RING_REG(RADEON_PP_TEX_PITCH_0, txpitch - 32);
442 OUT_RING_REG(RADEON_PP_TXFILTER_1, txfilter);
443 OUT_RING_REG(RADEON_PP_TXFORMAT_1, txformat);
445 OUT_RING_REG(RADEON_PP_TEX_SIZE_1,
448 OUT_RING_REG(RADEON_PP_TEX_PITCH_1, txpitch - 32);
642 OUT_RING_REG(RADEON_PP_CNTL, pp_cntl);
643 OUT_RING_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE)
    [all...]
radeon_exa_funcs.c 73 OUT_RING_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
74 OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
75 OUT_RING_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
76 OUT_RING_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
77 OUT_RING_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
78 OUT_RING_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
79 OUT_RING_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask);
80 OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
82 OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
86 OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset)
    [all...]
radeon.h 939 #define OUT_RING_REG(reg, val) \
1014 OUT_RING_REG((reg), (value)); \
1022 OUT_RING_REG((reg), (offset)); \
1028 OUT_RING_REG((reg), value); \
radeon_textured_video.c 181 #define OUT_ACCEL_REG_F(reg, val) OUT_RING_REG(reg, F_TO_DW(val))
  /xsrc/external/mit/xf86-video-r128/dist/src/
r128_exa.c 137 OUT_RING_REG( R128_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right );
138 OUT_RING_REG( R128_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl );
139 OUT_RING_REG( R128_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr );
140 OUT_RING_REG( R128_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr );
141 OUT_RING_REG( R128_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr );
142 OUT_RING_REG( R128_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr );
143 OUT_RING_REG( R128_DP_WRITE_MASK, info->state_2d.dp_write_mask );
144 OUT_RING_REG( R128_DP_CNTL, info->state_2d.dp_cntl );
146 OUT_RING_REG( R128_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset );
147 if (has_src) OUT_RING_REG( R128_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset )
    [all...]
r128_exa_render.c 386 OUT_RING_REG(R128_SCALE_3D_CNTL, \
392 OUT_RING_REG(R128_SETUP_CNTL, \
399 OUT_RING_REG(R128_PM4_VC_FPU_SETUP, \
412 OUT_RING_REG(R128_PLANE_3D_MASK_C, 0xffffffff); \
413 OUT_RING_REG(R128_CONSTANT_COLOR_C, 0xff000000); \
538 OUT_RING_REG(R128_MISC_3D_STATE_CNTL_REG,
543 OUT_RING_REG(R128_TEX_CNTL_C,
548 OUT_RING_REG(R128_PC_GUI_CTLSTAT, R128_PC_FLUSH_GUI);
r128.h 664 OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \
665 OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \
666 OUT_RING_REG( R128_AUX_SC_CNTL, info->aux_sc_cntl ); \
710 #define OUT_RING_REG( reg, val ) \
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_accel.c 612 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
900 OUT_RING_REG(RADEON_RBBM_GUICNTL,
903 OUT_RING_REG(RADEON_RBBM_GUICNTL,
906 OUT_RING_REG(RADEON_RBBM_GUICNTL,
radeon_exa.c 690 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
radeon_textured_video.c 172 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
radeon.h 1489 #define OUT_RING_REG(reg, val) \

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