Searched refs:QPU_GET_FIELD (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c39 return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w ||
40 QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w);
49 { QPU_GET_FIELD(inst, QPU_ADD_A) },
50 { QPU_GET_FIELD(inst, QPU_ADD_B) },
51 { QPU_GET_FIELD(inst, QPU_MUL_A) },
52 { QPU_GET_FIELD(inst, QPU_MUL_B) },
58 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH)
62 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
68 (QPU_GET_FIELD(inst, QPU_RADDR_A) == r))
72 QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu.c36 assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP ||
37 QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr);
42 assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP ||
43 QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) &&
44 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM);
49 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) {
50 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr);
53 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP);
288 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
289 uint32_t waddr_mul = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_disasm.c300 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
301 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
303 uint32_t pack = QPU_GET_FIELD(inst, QPU_PACK);
325 QPU_GET_FIELD(inst, QPU_RADDR_A) :
326 QPU_GET_FIELD(inst, QPU_RADDR_B));
327 uint32_t unpack = QPU_GET_FIELD(inst, QPU_UNPACK);
328 bool has_si = QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM;
329 uint32_t si = QPU_GET_FIELD(inst, QPU_SMALL_IMM);
364 uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
365 uint32_t cond = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_schedule.c135 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
206 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
209 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
210 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
211 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
212 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
213 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
326 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
327 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
328 uint32_t waddr_add = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_emit.c209 MAYBE_UNUSED uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
621 assert(QPU_GET_FIELD(*c->last_thrsw, QPU_SIG) ==
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
636 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
638 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
644 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
646 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
658 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
H A Dvc4_qpu_defines.h238 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c41 return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w ||
42 QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w);
51 { QPU_GET_FIELD(inst, QPU_ADD_A) },
52 { QPU_GET_FIELD(inst, QPU_ADD_B) },
53 { QPU_GET_FIELD(inst, QPU_MUL_A) },
54 { QPU_GET_FIELD(inst, QPU_MUL_B) },
60 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH)
64 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
70 (QPU_GET_FIELD(inst, QPU_RADDR_A) == r))
74 QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu.c36 assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP ||
37 QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr);
42 assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP ||
43 QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) &&
44 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM);
49 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) {
50 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr);
53 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP);
288 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
289 uint32_t waddr_mul = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_disasm.c300 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
301 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
303 uint32_t pack = QPU_GET_FIELD(inst, QPU_PACK);
325 QPU_GET_FIELD(inst, QPU_RADDR_A) :
326 QPU_GET_FIELD(inst, QPU_RADDR_B));
327 uint32_t unpack = QPU_GET_FIELD(inst, QPU_UNPACK);
328 bool has_si = QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM;
329 uint32_t si = QPU_GET_FIELD(inst, QPU_SMALL_IMM);
364 uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
365 uint32_t cond = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_schedule.c135 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
206 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
209 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
210 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
211 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
212 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
213 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
326 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
327 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
328 uint32_t waddr_add = QPU_GET_FIELD(ins
[all...]
H A Dvc4_qpu_emit.c209 ASSERTED uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
621 assert(QPU_GET_FIELD(*c->last_thrsw, QPU_SIG) ==
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
636 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
638 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
644 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
646 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
658 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
H A Dvc4_qpu_defines.h238 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c115 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
117 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
118 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
185 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
186 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
187 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
188 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
192 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
195 uint32_t add_b = QPU_GET_FIELD(ins
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c115 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
117 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
118 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
185 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
186 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
187 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
188 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
192 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
195 uint32_t add_b = QPU_GET_FIELD(ins
[all...]
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_pack.c41 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
745 uint32_t op = QPU_GET_FIELD(packed_inst, V3D_QPU_OP_ADD);
746 uint32_t mux_a = QPU_GET_FIELD(packed_inst, V3D_QPU_ADD_A);
747 uint32_t mux_b = QPU_GET_FIELD(packed_inst, V3D_QPU_ADD_B);
748 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
873 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
900 uint32_t op = QPU_GET_FIELD(packed_inst, V3D_QPU_OP_MUL);
901 uint32_t mux_a = QPU_GET_FIELD(packed_inst, V3D_QPU_MUL_A);
902 uint32_t mux_b = QPU_GET_FIELD(packed_inst, V3D_QPU_MUL_B);
963 instr->alu.mul.waddr = QPU_GET_FIELD(packed_ins
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_pack.c40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
715 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_ADD);
716 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A);
717 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_B);
718 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
842 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
869 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_MUL);
870 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A);
871 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_B);
931 instr->alu.mul.waddr = QPU_GET_FIELD(packed_ins
[all...]
/xsrc/external/mit/libdrm/dist/vc4/
H A Dvc4_qpu_defines.h218 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro

Completed in 21 milliseconds