Searched refs:QPU_MUX_B (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c122 else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
236 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
364 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
519 (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
532 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c122 else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
236 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
364 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
519 (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
532 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
/xsrc/external/mit/libdrm/dist/vc4/
H A Dvc4_qpu_defines.h145 QPU_MUX_B, enumerator in enum:qpu_mux
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu.c30 QPU_SET_FIELD(mux != QPU_MUX_SMALL_IMM ? mux : QPU_MUX_B, muxfield)
41 if (src.mux == QPU_MUX_B) {
90 if (dst.mux == QPU_MUX_B)
355 uint64_t mux_b_val = (uint64_t)QPU_MUX_B << mux_shift;
H A Dvc4_qpu_defines.h148 QPU_MUX_B, enumerator in enum:qpu_mux
H A Dvc4_qpu_emit.c88 src->mux = QPU_MUX_B;
168 uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux;
169 uint32_t mux1 = src1->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src1->mux;
H A Dvc4_qpu.h67 QPU_MUX_B,
H A Dvc4_qpu_validate.c73 src_regs[i].mux == QPU_MUX_B &&
H A Dvc4_qpu_disasm.c322 bool is_a = mux != QPU_MUX_B;
H A Dvc4_qpu_schedule.c220 if (mux != QPU_MUX_A && mux != QPU_MUX_B)
474 (src_muxes[i] == QPU_MUX_B &&
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu.c30 QPU_SET_FIELD(mux != QPU_MUX_SMALL_IMM ? mux : QPU_MUX_B, muxfield)
41 if (src.mux == QPU_MUX_B) {
90 if (dst.mux == QPU_MUX_B)
355 uint64_t mux_b_val = (uint64_t)QPU_MUX_B << mux_shift;
H A Dvc4_qpu_defines.h148 QPU_MUX_B, enumerator in enum:qpu_mux
H A Dvc4_qpu_emit.c88 src->mux = QPU_MUX_B;
168 uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux;
169 uint32_t mux1 = src1->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src1->mux;
H A Dvc4_qpu.h67 QPU_MUX_B,
H A Dvc4_qpu_validate.c75 src_regs[i].mux == QPU_MUX_B &&
H A Dvc4_qpu_disasm.c322 bool is_a = mux != QPU_MUX_B;
H A Dvc4_qpu_schedule.c220 if (mux != QPU_MUX_A && mux != QPU_MUX_B)
474 (src_muxes[i] == QPU_MUX_B &&

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