Searched refs:QPU_W_ACC0 (Results 1 - 13 of 13) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c308 if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
309 writes_reg(insts[i - 1], QPU_W_ACC0 + mux_b)) {
H A Dvc4_qpu_defines.h85 QPU_W_ACC0 = 32, /* aka r0 */ enumerator in enum:qpu_waddr
H A Dvc4_qpu_schedule.c246 case QPU_W_ACC0:
251 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
494 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
495 scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
496 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
497 scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
H A Dvc4_qpu_disasm.c163 [QPU_W_ACC0] = "r0",
H A Dvc4_qpu.c322 case QPU_W_ACC0:
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c310 if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
311 writes_reg(insts[i - 1], QPU_W_ACC0 + mux_b)) {
H A Dvc4_qpu_defines.h85 QPU_W_ACC0 = 32, /* aka r0 */ enumerator in enum:qpu_waddr
H A Dvc4_qpu_schedule.c246 case QPU_W_ACC0:
251 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
494 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
495 scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
496 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
497 scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
H A Dvc4_qpu_disasm.c163 [QPU_W_ACC0] = "r0",
H A Dvc4_qpu.c322 case QPU_W_ACC0:
/xsrc/external/mit/libdrm/dist/vc4/
H A Dvc4_qpu_defines.h82 QPU_W_ACC0 = 32, /* aka r0 */ enumerator in enum:qpu_waddr
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c106 return 64 + waddr - QPU_W_ACC0;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c106 return 64 + waddr - QPU_W_ACC0;

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