| /xsrc/external/mit/MesaLib/dist/src/util/sha1/ |
| sha1.c | 38 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
40 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
71 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
72 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/util/sha1/ |
| sha1.c | 38 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
40 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
71 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
72 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| hsw_sol.c | 112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
126 /* Double R0 (R0 = R0 + R0) */
129 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
130 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0));
132 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
135 /* Triple R0 (R1 = R0 + R0, R0 = R0 + R1) *
[all...] |
| hsw_queryobj.c | 41 MI_MATH_ALU2(LOAD, SRCA, R0),
42 MI_MATH_ALU2(LOAD, SRCB, R0),
71 MI_MATH_ALU2(STORE, R0, ACCU),
90 MI_MATH_ALU2(LOAD, SRCA, R0),
93 MI_MATH_ALU2(STORE, R0, ACCU),
118 MI_MATH_ALU2(LOAD, SRCA, R0),
119 MI_MATH_ALU2(LOAD, SRCB, R0),
121 MI_MATH_ALU2(STORE, R0, ACCU),
166 MI_MATH_ALU2(LOAD, SRCA, R0),
169 MI_MATH_ALU2(STOREINV, R0, ZF)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| hsw_sol.c | 112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
126 /* Double R0 (R0 = R0 + R0) */
129 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
130 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0));
132 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
135 /* Triple R0 (R1 = R0 + R0, R0 = R0 + R1) *
[all...] |
| hsw_queryobj.c | 43 MI_MATH_ALU2(LOAD, SRCA, R0),
44 MI_MATH_ALU2(LOAD, SRCB, R0),
73 MI_MATH_ALU2(STORE, R0, ACCU),
92 MI_MATH_ALU2(LOAD, SRCA, R0),
95 MI_MATH_ALU2(STORE, R0, ACCU),
120 MI_MATH_ALU2(LOAD, SRCA, R0),
121 MI_MATH_ALU2(LOAD, SRCB, R0),
123 MI_MATH_ALU2(STORE, R0, ACCU),
168 MI_MATH_ALU2(LOAD, SRCA, R0),
171 MI_MATH_ALU2(STOREINV, R0, ZF)
[all...] |
| brw_ff_gs.h | 79 struct brw_reg R0;
|
| brw_ff_gs_emit.c | 61 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
88 * Set up the initial value of c->reg.header register based on c->reg.R0.
90 * The following information is passed to the GS thread in R0, and needs to be
99 * R0 to the header register.
104 brw_MOV(p, c->reg.header, c->reg.R0);
122 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
132 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
390 get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
462 /* Now, reinitialize the header register from R0 to restore the parts of
503 get_element_ud(c->reg.R0, 2)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| brw_clip_util.c | 332 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
342 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
344 c->reg.R0,
365 c->reg.R0,
415 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
450 c->reg.R0,
452 c->reg.R0,
|
| brw_clip.h | 52 struct brw_reg R0;
|
| brw_compile_ff_gs.c | 45 struct brw_reg R0;
89 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
116 * Set up the initial value of c->reg.header register based on c->reg.R0.
118 * The following information is passed to the GS thread in R0, and needs to be
127 * R0 to the header register.
132 brw_MOV(p, c->reg.header, c->reg.R0);
150 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
160 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
419 get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
491 /* Now, reinitialize the header register from R0 to restore the parts o
[all...] |
| brw_clip_unfilled.c | 231 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
243 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
251 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
|
| brw_clip_line.c | 45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
150 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| brw_clip_tri.c | 52 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
141 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
179 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
635 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| brw_clip_util.c | 332 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
342 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
344 c->reg.R0,
365 c->reg.R0,
415 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
450 c->reg.R0,
452 c->reg.R0,
|
| brw_clip.h | 52 struct brw_reg R0;
|
| brw_clip_unfilled.c | 231 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
243 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
251 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
|
| brw_clip_line.c | 45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
150 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| brw_clip_tri.c | 52 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
141 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
179 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
635 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/ |
| iris_query.c | 422 /* Store ACCU to R1 and add R0 to R1 */
527 MI_ALU2(LOAD, SRCA, R0),
530 MI_ALU2(STOREINV, R0, ZF),
531 MI_ALU2(LOAD, SRCA, R0),
534 MI_ALU2(STORE, R0, ACCU),
567 * R0 = R0 | R1;
588 MI_ALU2(LOAD, SRCB, R0),
590 MI_ALU2(STORE, R0, ACCU),
627 MI_ALU2(LOAD, SRCA, R0),
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/rtasm/ |
| rtasm_x86sse.c | 100 #define DUMP_R( R0 ) do { \
102 x86_print_reg( R0 ); \
105 #define DUMP_RR( R0, R1 ) do { \
107 x86_print_reg( R0 ); \
112 #define DUMP_RI( R0, I ) do { \
114 x86_print_reg( R0 ); \
118 #define DUMP_RRI( R0, R1, I ) do { \
120 x86_print_reg( R0 ); \
132 #define DUMP_R( R0 )
133 #define DUMP_RR( R0, R1
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/rtasm/ |
| rtasm_x86sse.c | 100 #define DUMP_R( R0 ) do { \
102 x86_print_reg( R0 ); \
105 #define DUMP_RR( R0, R1 ) do { \
107 x86_print_reg( R0 ); \
112 #define DUMP_RI( R0, I ) do { \
114 x86_print_reg( R0 ); \
118 #define DUMP_RRI( R0, R1, I ) do { \
120 x86_print_reg( R0 ); \
132 #define DUMP_R( R0 )
133 #define DUMP_RR( R0, R1
[all...] |
| /xsrc/external/mit/MesaLib/dist/docs/_extra/specs/OLD/ |
| MESA_program_debug.spec | 312 be used to print the values of R0, R1, R2 and R3 while executing
|
| /xsrc/external/mit/MesaLib.old/dist/docs/specs/OLD/ |
| MESA_program_debug.spec | 312 be used to print the values of R0, R1, R2 and R3 while executing
|
| /xsrc/external/mit/xf86-video-tdfx/dist/src/ |
| tdfx_priv.h | 173 ** e.g. R5 = baseReg + 5, R0 = baseReg etc..
175 #define R0 (1 << 0)
|
