Searched refs:R200_TXC_CLAMP_0_1 (Results 1 - 14 of 14) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 174 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
197 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
229 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
245 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 |
261 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 |
277 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 |
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| H A D | r200_fragshader.c | 286 SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_0_1;
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| H A D | r200_reg.h | 1248 #define R200_TXC_CLAMP_0_1 (1 << 12) macro
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| H A D | r200_state_init.c | 1103 R200_TXC_CLAMP_0_1 |
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 161 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
187 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
219 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
235 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 |
251 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 |
267 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 |
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| H A D | r200_fragshader.c | 288 SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_0_1;
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| H A D | r200_reg.h | 1248 #define R200_TXC_CLAMP_0_1 (1 << 12) macro
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| H A D | r200_state_init.c | 1103 R200_TXC_CLAMP_0_1 |
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| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 851 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
955 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
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| H A D | radeon_exa_render.c | 1117 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
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| H A D | radeon_reg.h | 2894 # define R200_TXC_CLAMP_0_1 (1 << 12) macro
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| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 678 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
782 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
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| H A D | radeon_exa_render.c | 1057 R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
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| H A D | radeon_reg.h | 2894 # define R200_TXC_CLAMP_0_1 (1 << 12) macro
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