Searched refs:RADEON_ENC_BEGIN (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc_1_1.c41 #define RADEON_ENC_BEGIN(cmd) { \ macro
214 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
231 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
252 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
268 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
279 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
295 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
321 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
360 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
384 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INI
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H A Dradeon_vcn_enc_1_2.c42 #define RADEON_ENC_BEGIN(cmd) { \ macro
190 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
205 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
222 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
243 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
259 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
269 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
279 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
291 RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
308 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MIS
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc_1_1.c39 #define RADEON_ENC_BEGIN(cmd) \ macro
197 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
213 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
231 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
246 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
256 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
269 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
290 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
323 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
342 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INI
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H A Dradeon_vcn_enc_3_0.c53 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
73 RADEON_ENC_BEGIN(enc->cmd.quality_params);
90 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
115 RADEON_ENC_BEGIN(enc->cmd.nalu);
H A Dradeon_vcn_enc_1_2.c68 RADEON_ENC_BEGIN(enc->cmd.session_info);
84 RADEON_ENC_BEGIN(enc->cmd.task_info);
103 RADEON_ENC_BEGIN(enc->cmd.session_init);
126 RADEON_ENC_BEGIN(enc->cmd.session_init);
142 RADEON_ENC_BEGIN(enc->cmd.layer_control);
152 RADEON_ENC_BEGIN(enc->cmd.layer_select);
163 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
177 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
194 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
207 RADEON_ENC_BEGIN(en
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H A Dradeon_vcn_enc_2_0.c78 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE);
90 RADEON_ENC_BEGIN(enc->cmd.slice_header);
224 RADEON_ENC_BEGIN(enc->cmd.quality_params);
234 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
247 RADEON_ENC_BEGIN(enc->cmd.nalu);
350 RADEON_ENC_BEGIN(enc->cmd.nalu);
408 RADEON_ENC_BEGIN(enc->cmd.input_format);
431 RADEON_ENC_BEGIN(enc->cmd.output_format);
470 RADEON_ENC_BEGIN(enc->cmd.ctx);
H A Dradeon_vcn_enc.h132 #define RADEON_ENC_BEGIN(cmd) \ macro

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