Searched refs:RADEON_PPLL_DIV_3 (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dlegacy_crtc.c325 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) &
378 OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
382 OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
603 save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3);
H A Dradeon_reg.h1462 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h980 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h980 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ macro
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_reg.h1462 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ macro

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