Searched refs:R_028644_SPI_PS_INPUT_CNTL_0 (Results 1 - 19 of 19) sorted by relevance
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| H A D | ac_shadowed_regs.c | 96 R_028644_SPI_PS_INPUT_CNTL_0,
97 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
311 R_028644_SPI_PS_INPUT_CNTL_0,
312 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
639 R_028644_SPI_PS_INPUT_CNTL_0,
640 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
1512 set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Gfx9));
2214 set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Nv10));
2912 set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Gfx103));
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| /xsrc/external/mit/MesaLib.old/src/gallium/drivers/r600/ |
| H A D | egd_tables.h | 940 {15179, R_028644_SPI_PS_INPUT_CNTL_0, 8, 414},
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| /xsrc/external/mit/MesaLib/src/gallium/drivers/r600/ |
| H A D | egd_tables.h | 940 {15179, R_028644_SPI_PS_INPUT_CNTL_0, 8, 414},
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state_draw.cpp | 99 /* R_028644_SPI_PS_INPUT_CNTL_0 */
103 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600d.h | 1512 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
2423 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| H A D | evergreend.h | 1827 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| H A D | r600_state.c | 2454 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
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| H A D | evergreen_state.c | 3395 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600d.h | 1512 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
2423 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| H A D | evergreend.h | 1827 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| H A D | r600_state.c | 2457 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
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| H A D | evergreen_state.c | 3408 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state_shaders.c | 2872 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2876 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
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| /xsrc/external/mit/MesaLib.old/src/amd/common/ |
| H A D | sid_tables.h | 1068 {20418, R_028644_SPI_PS_INPUT_CNTL_0, 12, 1350},
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_pipeline.c | 3307 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_pipeline.c | 5013 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| H A D | gfx9d.h | 4628 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| H A D | sid.h | 5947 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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| /xsrc/external/mit/MesaLib/src/amd/common/ |
| H A D | amdgfxregs.h | 9542 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
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