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    Searched refs:SR06 (Results 1 - 3 of 3) sorted by relevancy

  /xsrc/external/mit/xf86-video-tseng/dist/src/
tseng.h 78 CARD8 SR06, SR07;
tseng_mode.c 1088 tsengReg->SR06 = hwp->readSeq(hwp, 0x06);
1198 hwp->writeSeq(hwp, 0x06, tsengReg->SR06);
1322 new->SR06 = 0x00;
  /xsrc/external/mit/xf86-video-xgi/dist/src/
vb_setmode.c 4386 UCHAR SR01 = 0, SR1F = 0, SR07 = 0, SR06 = 0;
4420 SR06 = (UCHAR) XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x06);
4421 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x06, (UCHAR) (SR06 & 0xC3));
4542 /* Copy SR06 to 2nd chip */
8028 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3c4 , 0x06 , ~0x40 , temp ) ; /* SR06[6] 18bit Dither */
8040 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3c4 , 0x06 , ~0xc0 , temp & 0x80 ) ; /* SR06[7]0: dual 12/1: single 24 [6] 18bit Dither <= 0 h/w recommend */

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