Searched refs:SSE2 (Results 1 - 16 of 16) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_cpu.c79 features |= SSE2;
102 if (features & SSE2)
H A Dgen2_render.c2028 if (sna->cpu_features & SSE2) {
2041 if (sna->cpu_features & SSE2) {
2051 if (sna->cpu_features & SSE2) {
2061 if (sna->cpu_features & SSE2) {
2073 if (sna->cpu_features & SSE2) {
2634 if (sna->cpu_features & SSE2) {
2644 if (sna->cpu_features & SSE2) {
2656 if (sna->cpu_features & SSE2) {
2667 if (sna->cpu_features & SSE2) {
H A Dgen3_render.c3712 if (sna->cpu_features & SSE2) {
3727 if (sna->cpu_features & SSE2) {
3739 if (sna->cpu_features & SSE2) {
3754 if (sna->cpu_features & SSE2) {
3765 if (sna->cpu_features & SSE2) {
3779 if (sna->cpu_features & SSE2) {
3796 if (sna->cpu_features & SSE2) {
3805 if (sna->cpu_features & SSE2) {
3815 if (sna->cpu_features & SSE2) {
3826 if (sna->cpu_features & SSE2) {
[all...]
H A Dblt.c49 sse2_present = sna_cpu_detect() & SSE2;
1175 if (cpu & SSE2) {
H A Dsna.h276 #define SSE2 0x4 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_cpu.c79 features |= SSE2;
102 if (features & SSE2)
H A Dblt.c48 SSE2 = 0x8, enumerator in enum:__anon0d4246100103
103 features |= SSE2;
116 sse2_present = detect_cpu_features() & SSE2;
H A Dgen2_render.c2001 if (sna->cpu_features & SSE2) {
2014 if (sna->cpu_features & SSE2) {
2024 if (sna->cpu_features & SSE2) {
2034 if (sna->cpu_features & SSE2) {
2046 if (sna->cpu_features & SSE2) {
2603 if (sna->cpu_features & SSE2) {
2613 if (sna->cpu_features & SSE2) {
2625 if (sna->cpu_features & SSE2) {
2636 if (sna->cpu_features & SSE2) {
H A Dgen3_render.c3661 if (sna->cpu_features & SSE2) {
3676 if (sna->cpu_features & SSE2) {
3688 if (sna->cpu_features & SSE2) {
3703 if (sna->cpu_features & SSE2) {
3714 if (sna->cpu_features & SSE2) {
3728 if (sna->cpu_features & SSE2) {
3745 if (sna->cpu_features & SSE2) {
3754 if (sna->cpu_features & SSE2) {
3764 if (sna->cpu_features & SSE2) {
3775 if (sna->cpu_features & SSE2) {
[all...]
H A Dsna.h260 #define SSE2 0x4 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/
H A Disa.hpp78 bool SSE2(void) { return CPU_Rep.f_1_EDX_[26]; } function in class:InstructionSet
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/
H A Disa.hpp78 bool SSE2(void) { return CPU_Rep.f_1_EDX_[26]; } function in class:InstructionSet
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D8.0.2.rst110 - gallium/rtasm: properly detect SSE and SSE2
H A D7.10.rst1836 - llvmpipe: Fix MSVC build. Enable the new SSE2 code on non SSE3
1958 - llvmpipe: simplified SSE2 swz/unswz routines
H A D21.2.0.rst4678 - Default enable SSE2 on mesa builds.
/xsrc/external/mit/MesaLib/dist/docs/drivers/
H A Dllvmpipe.rst18 SSE2 is strongly encouraged. Support for SSE3 and SSE4.1 will yield

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