Searched refs:SVGA_REG_SYNC (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-vmware/dist/src/
H A Dsvga_reg.h144 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ enumerator in enum:__anon2480ccb20103
628 * SVGA_REG_SYNC --
679 * This register is set to TRUE when SVGA_REG_SYNC is written,
720 * 3. Write a reason to SVGA_REG_SYNC. This will send an
H A Dvmware.c202 vmwareWriteReg(pVMWARE, SVGA_REG_SYNC, 1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/include/
H A Dsvga_reg.h151 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ enumerator in enum:__anonea0e1c880203
874 * SVGA_REG_SYNC --
925 * This register is set to TRUE when SVGA_REG_SYNC is written,
966 * 3. Write a reason to SVGA_REG_SYNC. This will send an
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/include/
H A Dsvga_reg.h151 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ enumerator in enum:__anon6cda5f7b0203
874 * SVGA_REG_SYNC --
925 * This register is set to TRUE when SVGA_REG_SYNC is written,
966 * 3. Write a reason to SVGA_REG_SYNC. This will send an

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