Searched refs:VARYING_BIT_TESS_LEVEL_OUTER (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_tes.c144 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
204 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
H A Dbrw_link.cpp177 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
179 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_tes.c147 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
206 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
H A Dbrw_link.cpp177 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
179 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vue_map.c210 vertex_slots &= ~(VARYING_BIT_TESS_LEVEL_OUTER |
H A Dbrw_nir.c1090 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vue_map.c227 vertex_slots &= ~(VARYING_BIT_TESS_LEVEL_OUTER |
H A Dbrw_nir.c1492 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib.old/dist/src/compiler/
H A Dshader_enums.h339 #define VARYING_BIT_TESS_LEVEL_OUTER BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER) macro
/xsrc/external/mit/MesaLib/dist/src/compiler/
H A Dshader_enums.h458 #define VARYING_BIT_TESS_LEVEL_OUTER BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER) macro
/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/
H A Dst_glsl_to_nir.cpp892 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
894 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_pipeline.c1699 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
1701 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_pipeline.c1996 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c3065 (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));

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