Searched refs:WRITE_REG32 (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Ddisp_gu2.c124 WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
125 WRITE_REG32(MDC_DISPLAY_CFG, dcfg);
126 WRITE_REG32(MDC_UNLOCK, lock);
200 WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
211 WRITE_REG32(MDC_DISPLAY_CFG, dcfg);
220 WRITE_REG32(MDC_GENERAL_CFG, gcfg);
236 WRITE_REG32(MDC_FB_ST_OFFSET, 0);
237 WRITE_REG32(MDC_CB_ST_OFFSET, 0);
238 WRITE_REG32(MDC_CURS_ST_OFFSET, 0);
239 WRITE_REG32(MDC_ICON_ST_OFFSE
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H A Ddisp_gu1.c197 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
205 WRITE_REG32(DC_TIMING_CFG, tcfg);
214 WRITE_REG32(DC_GENERAL_CFG, gcfg);
215 WRITE_REG32(DC_UNLOCK, unlock);
246 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
247 WRITE_REG32(DC_OUTPUT_CFG, ocfg);
248 WRITE_REG32(DC_UNLOCK, lock);
291 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
299 WRITE_REG32(DC_TIMING_CFG, tcfg);
309 WRITE_REG32(DC_GENERAL_CF
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H A Drndr_gu1.c112 WRITE_REG32(GP_BLIT_STATUS, control);
281 WRITE_REG32(GP_PAT_DATA_0, data0);
282 WRITE_REG32(GP_PAT_DATA_1, data1);
331 WRITE_REG32(GP_PAT_DATA_0, data0);
332 WRITE_REG32(GP_PAT_DATA_1, data1);
334 WRITE_REG32(GP_PAT_DATA_2, data2);
335 WRITE_REG32(GP_PAT_DATA_3, data3);
372 WRITE_REG32(GP_PAT_DATA_0, pattern_8x8[0]);
373 WRITE_REG32(GP_PAT_DATA_1, pattern_8x8[1]);
375 WRITE_REG32(GP_PAT_DATA_
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H A Dgfx_defs.h42 #define WRITE_REG32(offset, value) \ macro
H A Dtv_fs450.c294 WRITE_REG32(phys_addr, data);
/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Ddisp_gu2.c351 WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
352 WRITE_REG32(MDC_DISPLAY_CFG, dcfg);
353 WRITE_REG32(MDC_UNLOCK, lock);
434 WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
448 WRITE_REG32(MDC_DISPLAY_CFG, dcfg);
459 WRITE_REG32(MDC_GENERAL_CFG, gcfg);
478 WRITE_REG32(MDC_FB_ST_OFFSET, 0);
479 WRITE_REG32(MDC_CB_ST_OFFSET, 0);
480 WRITE_REG32(MDC_CURS_ST_OFFSET, 0);
481 WRITE_REG32(MDC_ICON_ST_OFFSE
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H A Ddisp_gu1.c416 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
426 WRITE_REG32(DC_TIMING_CFG, tcfg);
437 WRITE_REG32(DC_GENERAL_CFG, gcfg);
438 WRITE_REG32(DC_UNLOCK, unlock);
470 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
471 WRITE_REG32(DC_OUTPUT_CFG, ocfg);
472 WRITE_REG32(DC_UNLOCK, lock);
522 WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
532 WRITE_REG32(DC_TIMING_CFG, tcfg);
544 WRITE_REG32(DC_GENERAL_CF
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H A Drndr_gu1.c262 WRITE_REG32(GP_BLIT_STATUS, control);
431 WRITE_REG32(GP_PAT_DATA_0, data0);
432 WRITE_REG32(GP_PAT_DATA_1, data1);
481 WRITE_REG32(GP_PAT_DATA_0, data0);
482 WRITE_REG32(GP_PAT_DATA_1, data1);
484 WRITE_REG32(GP_PAT_DATA_2, data2);
485 WRITE_REG32(GP_PAT_DATA_3, data3);
522 WRITE_REG32(GP_PAT_DATA_0, pattern_8x8[0]);
523 WRITE_REG32(GP_PAT_DATA_1, pattern_8x8[1]);
525 WRITE_REG32(GP_PAT_DATA_
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H A Dgfx_defs.h146 #define WRITE_REG32(offset, value) \ macro
H A Dtv_fs450.c434 WRITE_REG32(phys_addr, data);
/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vg.c637 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
661 WRITE_REG32(DC3_GENERAL_CFG, (temp & ~DC3_GCFG_VIDE));
667 WRITE_REG32(DC3_IRQ, DC3_IRQ_MASK | DC3_VSYNC_IRQ_MASK |
673 WRITE_REG32(DC3_GENLK_CTL, (genlk_ctl & ~DC3_GC_GENLOCK_ENABLE));
687 WRITE_REG32(DC3_COLOR_KEY, (temp & ~DC3_CLR_KEY_ENABLE));
708 WRITE_REG32(DC3_GENERAL_CFG, gcfg);
714 WRITE_REG32(DC3_DISPLAY_CFG, dcfg);
723 WRITE_REG32(DC3_GENERAL_CFG, gcfg);
762 WRITE_REG32(DC3_FB_ST_OFFSET, 0);
763 WRITE_REG32(DC3_CB_ST_OFFSE
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H A Dcim_vop.c49 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
96 WRITE_REG32(DC3_VBI_HOR, ((hstop << DC3_VBI_HOR_END_SHIFT) &
102 WRITE_REG32(DC3_VBI_LN_ODD, ((buffer->odd_line_offset <<
107 WRITE_REG32(DC3_VBI_LN_EVEN, ((buffer->even_line_offset <<
121 WRITE_REG32(DC3_VBI_EVEN_CTL, temp |
127 WRITE_REG32(DC3_VBI_ODD_CTL, temp |
134 WRITE_REG32(DC3_VBI_PITCH, temp);
136 WRITE_REG32(DC3_UNLOCK, unlock);
160 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
161 WRITE_REG32(DC3_VBI_EVEN_CT
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H A Dcim_df.c253 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
257 WRITE_REG32(DC3_GENERAL_CFG, gcfg);
258 WRITE_REG32(DC3_LINE_SIZE, vg_line);
259 WRITE_REG32(DC3_VID_YUV_PITCH, pitch);
265 WRITE_REG32(DC3_VID_EVEN_Y_ST_OFFSET, video_source_even->y_offset);
266 WRITE_REG32(DC3_VID_EVEN_U_ST_OFFSET, video_source_even->u_offset);
267 WRITE_REG32(DC3_VID_EVEN_V_ST_OFFSET, video_source_even->v_offset);
270 WRITE_REG32(DC3_VID_Y_ST_OFFSET, video_source_odd->y_offset);
271 WRITE_REG32(DC3_VID_U_ST_OFFSET, video_source_odd->u_offset);
272 WRITE_REG32(DC3_VID_V_ST_OFFSE
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H A Dcim_vip.c708 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
709 WRITE_REG32(DC3_GENLK_CTL, genlk_ctl);
712 WRITE_REG32(DC3_UNLOCK, unlock);
736 WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE);
737 WRITE_REG32(DC3_GENLK_CTL, temp);
738 WRITE_REG32(DC3_UNLOCK, unlock);
H A Dcim_defs.h52 #define WRITE_REG32(offset, value) \ macro
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_gx1_accel.c1059 WRITE_REG32(GP_SRC_COLOR_0, (planemask << 16) | planemask);
1115 WRITE_REG32(GP_DST_XCOOR, (y << 16) | x);
1138 WRITE_REG32(GP_DST_XCOOR, (y << 16) | (x + section));
1272 WRITE_REG32(GP_DST_XCOOR, 0);
1273 WRITE_REG32(GP_SRC_XCOOR, 0);
1274 WRITE_REG32(GP_WIDTH, 0x00010001);
1283 WRITE_REG32(GP_PAT_COLOR_0, 0xFFFFFFFF);
1562 WRITE_REG32(GP_DST_XCOOR, (y1 << 16) | x1);
1563 WRITE_REG32(GP_VECTOR_LENGTH, (((unsigned long)init) << 16) |
1565 WRITE_REG32(GP_AXIAL_ERRO
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H A Dnsc_regacc.c183 WRITE_REG32(offset, value);
H A Dnsc_gx2_driver.c1151 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);
/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dgx_regacc.c93 WRITE_REG32(offset, value);
H A Dgx_driver.c823 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);

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