| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| radeon_video.c | 162 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
177 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
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| evergreen_state.c | 736 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local
815 bankw = tmp->surface.u.legacy.bankw;
819 bankw = eg_bank_wh(bankw);
903 S_03001C_BANK_WIDTH(bankw) |
1126 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local
1164 bankw = rtex->surface.u.legacy.bankw;
1172 bankw = eg_bank_wh(bankw)
1362 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
[all...] |
| r600_texture.c | 284 metadata->u.legacy.bankw = surface->u.legacy.bankw;
300 surf->u.legacy.bankw = metadata->u.legacy.bankw;
609 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
838 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
840 rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw,
|
| radeon_uvd.c | 1241 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
1246 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| radeon_video.c | 162 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
177 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
|
| evergreen_state.c | 730 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local
809 bankw = tmp->surface.u.legacy.bankw;
813 bankw = eg_bank_wh(bankw);
897 S_03001C_BANK_WIDTH(bankw) |
1120 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local
1158 bankw = rtex->surface.u.legacy.bankw;
1166 bankw = eg_bank_wh(bankw)
1356 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
[all...] |
| r600_texture.c | 285 metadata->u.legacy.bankw = surface->u.legacy.bankw;
301 surf->u.legacy.bankw = metadata->u.legacy.bankw;
614 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
843 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
845 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| radeon_video.c | 151 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
168 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
|
| radeon_winsys.h | 209 unsigned bankw; member in struct:radeon_bo_metadata::__anon4022::__anon4023
|
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| evergreen_accel.c | 209 uint32_t tile_split, macro_aspect, bankw, bankh; local
231 bankw = cb_conf->surface->bankw;
235 bankw = eg_bank_wh(bankw);
247 bankw = 0;
255 (bankw << CB_COLOR0_ATTRIB__BANK_WIDTH_shift) |
699 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local
717 bankw = tex_res->surface->bankw;
[all...] |
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| evergreen_accel.c | 206 uint32_t tile_split, macro_aspect, bankw, bankh; local
227 bankw = cb_conf->surface->bankw;
231 bankw = eg_bank_wh(bankw);
241 bankw = 0;
249 (bankw << CB_COLOR0_ATTRIB__BANK_WIDTH_shift) |
691 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local
708 bankw = tex_res->surface->bankw;
[all...] |
| radeon_bo_helper.c | 154 surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
281 tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 151 surf_drm->bankw = surf_ws->u.legacy.bankw;
193 surf_ws->u.legacy.bankw = surf_drm->bankw;
|
| /xsrc/external/mit/libdrm/dist/radeon/ |
| radeon_surface.h | 124 * overridden (things lile bankw/bankh on evergreen for
130 uint32_t bankw; member in struct:radeon_surface
|
| radeon_surface.c | 675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
760 switch (surf->bankw) {
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
905 /* compute best tile_split, bankw, bankh, mtilea
919 surf->bankw = 1;
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
978 /* bankw or bankh greater than 1 increase alignment requirement, not
979 * sure if it's worth using smaller bankw & bankh to stick with 2D
995 /* use bankw of 1 to minimize width alignment, might be interesting to
998 surf->bankw = 1
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 151 surf_drm->bankw = surf_ws->u.legacy.bankw;
193 surf_ws->u.legacy.bankw = surf_drm->bankw;
|
| radeon_drm_bo.c | 904 surf->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
927 md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
955 args.tiling_flags |= (surf->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) <<
980 args.tiling_flags |= (md->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) <<
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| ac_surface.h | 95 unsigned bankw:4; /* max 8 */ member in struct:legacy_surf_layout
190 * they will be treated as hints (e.g. bankw, bankh) and might be
|
| ac_surface.c | 518 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
778 surf->u.legacy.bankw && surf->u.legacy.bankh &&
783 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_radeon_winsys.h | 142 unsigned bankw; member in struct:radeon_bo_metadata::__anon3266::__anon3267
|
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_surface.h | 114 unsigned bankw : 4; /* max 8 */ member in struct:legacy_surf_layout
326 * they will be treated as hints (e.g. bankw, bankh) and might be
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_radeon_winsys.h | 134 unsigned bankw; member in struct:radeon_bo_metadata::__anon582::__anon583
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| radeon_winsys.h | 228 unsigned bankw; member in struct:radeon_bo_metadata::__anon1579::__anon1580
|
| radeon_uvd.c | 1474 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
1479 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_bo.c | 672 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
717 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
|
