Searched refs:bind_map (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_pipeline_cache.c43 const struct anv_pipeline_bind_map *bind_map)
60 bind_map->surface_count);
62 bind_map->sampler_count);
141 shader->bind_map = *bind_map;
142 typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
143 bind_map->surface_count);
144 shader->bind_map.surface_to_descriptor = surface_to_descriptor;
145 typed_memcpy(sampler_to_descriptor, bind_map->sampler_to_descriptor,
146 bind_map
35 anv_shader_bin_create(struct anv_device * device,gl_shader_stage stage,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data_in,uint32_t prog_data_size,const struct brw_compile_stats * stats,uint32_t num_stats,const nir_xfb_info * xfb_info_in,const struct anv_pipeline_bind_map * bind_map) argument
245 struct anv_pipeline_bind_map bind_map; local in function:anv_shader_bin_create_from_blob
428 anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache * cache,gl_shader_stage stage,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const struct brw_compile_stats * stats,uint32_t num_stats,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
460 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache * cache,gl_shader_stage stage,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const struct brw_compile_stats * stats,uint32_t num_stats,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
720 anv_device_upload_kernel(struct anv_device * device,struct anv_pipeline_cache * cache,gl_shader_stage stage,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const struct brw_compile_stats * stats,uint32_t num_stats,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
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H A Danv_pipeline.c608 struct anv_pipeline_bind_map bind_map; member in struct:anv_pipeline_stage
838 layout, nir, &stage->bind_map);
867 nir, prog_data, &stage->bind_map, mem_ctx);
1116 assert(stage->bind_map.surface_count == 0);
1117 typed_memcpy(stage->bind_map.surface_to_descriptor,
1119 stage->bind_map.surface_count += num_rt_bindings;
1256 push_size += stage->bind_map.push_ranges[i].length;
1260 if (stage->bind_map.push_ranges[i].length == 0)
1264 stage->bind_map.push_ranges[i].length * 32);
1266 switch (stage->bind_map
3008 struct anv_pipeline_bind_map bind_map = { local in function:anv_device_init_rt_shaders
3061 struct anv_pipeline_bind_map bind_map = { local in function:anv_device_init_rt_shaders
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H A DgenX_pipeline.c1223 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
1716 uint32_t count_by_4 = DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
1793 vs.BindingTableEntryCount = vs_bin->bind_map.surface_count;
1870 hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
1952 ds.BindingTableEntryCount = tes_bin->bind_map.surface_count;
2015 gs.BindingTableEntryCount = gs_bin->bind_map.surface_count;
2075 const struct anv_pipeline_bind_map *bind_map = &shader_bin->bind_map; local in function:has_color_buffer_write_enabled
2076 for (int i = 0; i < bind_map->surface_count; i++) {
2077 struct anv_pipeline_binding *binding = &bind_map
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H A DgenX_cmd_buffer.c2573 struct anv_pipeline_bind_map *map = &shader->bind_map;
2885 struct anv_pipeline_bind_map *map = &shader->bind_map;
3205 const struct anv_pipeline_bind_map *bind_map = local in function:cmd_buffer_emit_push_constant
3206 &pipeline->shaders[stage]->bind_map;
3241 const struct anv_push_range *range = &bind_map->push_ranges[i];
3259 if (bind_map->push_ranges[0].length > 0) {
3261 assert(bind_map->push_ranges[0].set ==
3265 c.ConstantBody.ReadLength[0] = bind_map->push_ranges[0].length;
3269 assert(bind_map->push_ranges[1].length == 0);
3270 assert(bind_map
3308 const struct anv_pipeline_bind_map *bind_map = local in function:cmd_buffer_emit_push_constant_all
3353 const struct anv_pipeline_bind_map *bind_map = &shader->bind_map; local in function:cmd_buffer_flush_push_constants
3398 const struct anv_pipeline_bind_map *bind_map = &shader->bind_map; local in function:cmd_buffer_flush_push_constants
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H A Danv_cmd_buffer.c496 &compute_pipeline->cs->bind_map);
512 &gfx_pipeline->shaders[stage]->bind_map);
1175 const struct anv_push_range *range = &pipeline->cs->bind_map.push_ranges[0];
H A Dgfx7_cmd_buffer.c426 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
H A Danv_private.h1112 const struct anv_pipeline_bind_map *bind_map);
1131 const struct anv_pipeline_bind_map *bind_map);
3450 struct anv_pipeline_bind_map bind_map; member in struct:anv_shader_bin
3462 const struct anv_pipeline_bind_map *bind_map);
H A Dgfx8_cmd_buffer.c729 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
H A Danv_blorp.c67 struct anv_pipeline_bind_map bind_map = { local in function:upload_blorp_shader
76 NULL, 0, NULL, &bind_map);
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_pipeline_cache.c41 const struct anv_pipeline_bind_map *bind_map)
60 bind_map->surface_count);
62 bind_map->sampler_count);
105 shader->bind_map = *bind_map;
106 typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
107 bind_map->surface_count);
108 shader->bind_map.surface_to_descriptor = surface_to_descriptor;
109 typed_memcpy(sampler_to_descriptor, bind_map->sampler_to_descriptor,
110 bind_map
34 anv_shader_bin_create(struct anv_device * device,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const void * constant_data,uint32_t constant_data_size,const struct brw_stage_prog_data * prog_data_in,uint32_t prog_data_size,const void * prog_data_param_in,const nir_xfb_info * xfb_info_in,const struct anv_pipeline_bind_map * bind_map) argument
193 struct anv_pipeline_bind_map bind_map; local in function:anv_shader_bin_create_from_blob
353 anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache * cache,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const void * constant_data,uint32_t constant_data_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const void * prog_data_param,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
385 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache * cache,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const void * constant_data,uint32_t constant_data_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
654 anv_device_upload_kernel(struct anv_device * device,struct anv_pipeline_cache * cache,const void * key_data,uint32_t key_size,const void * kernel_data,uint32_t kernel_size,const void * constant_data,uint32_t constant_data_size,const struct brw_stage_prog_data * prog_data,uint32_t prog_data_size,const nir_xfb_info * xfb_info,const struct anv_pipeline_bind_map * bind_map) argument
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H A Danv_pipeline.c441 struct anv_pipeline_bind_map bind_map; member in struct:anv_pipeline_stage
622 &stage->bind_map);
918 assert(stage->bind_map.surface_count == 0);
919 typed_memcpy(stage->bind_map.surface_to_descriptor,
921 stage->bind_map.surface_count += num_rts;
1110 stages[s].bind_map = (struct anv_pipeline_bind_map) {
1212 xfb_info, &stages[s].bind_map);
1317 stage.bind_map = (struct anv_pipeline_bind_map) {
1323 stage.bind_map.surface_count = 1;
1324 stage.bind_map
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H A DgenX_pipeline.c912 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
1283 uint32_t count_by_4 = DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
1295 return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
1587 const struct anv_pipeline_bind_map *bind_map = &shader_bin->bind_map; local in function:has_color_buffer_write_enabled
1588 for (int i = 0; i < bind_map->surface_count; i++) {
1589 struct anv_pipeline_binding *binding = &bind_map->surface_to_descriptor[i];
2122 * for in bind_map.surface_count.
2124 .BindingTableEntryCount = GEN_GEN == 11 ? 0 : 1 + MIN2(cs_bin->bind_map.surface_count, 30),
H A Danv_private.h1062 const struct anv_pipeline_bind_map *bind_map);
1080 const struct anv_pipeline_bind_map *bind_map);
2707 struct anv_pipeline_bind_map bind_map; member in struct:anv_shader_bin
2718 const struct anv_pipeline_bind_map *bind_map);
H A DgenX_cmd_buffer.c2054 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2310 struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
2472 const struct anv_pipeline_bind_map *bind_map = local in function:cmd_buffer_flush_push_constants
2473 &pipeline->shaders[stage]->bind_map;
2496 assert(surface <= bind_map->surface_count);
2498 &bind_map->surface_to_descriptor[surface];
H A Danv_blorp.c67 struct anv_pipeline_bind_map bind_map = { local in function:upload_blorp_shader
77 NULL, &bind_map);

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