| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| i965_3d.c | 139 uint32_t blend_offset)
144 blend_offset | 1);
164 uint32_t blend_offset)
169 blend_offset | 1);
|
| intel_uxa.h | 161 uint32_t blend_offset);
165 uint32_t blend_offset);
|
| i965_render.c | 2594 uint32_t blend_offset)
2600 if (intel->gen6_render_state.blend == blend_offset)
2608 gen7_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset);
2610 gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset);
2613 intel->gen6_render_state.blend = blend_offset;
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| i965_3d.c | 139 uint32_t blend_offset)
144 blend_offset | 1);
164 uint32_t blend_offset)
169 blend_offset | 1);
|
| intel_uxa.h | 161 uint32_t blend_offset);
165 uint32_t blend_offset);
|
| i965_render.c | 2594 uint32_t blend_offset)
2600 if (intel->gen6_render_state.blend == blend_offset)
2608 gen7_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset);
2610 gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset);
2613 intel->gen6_render_state.blend = blend_offset;
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| gen7_render.c | 310 #define BLEND_OFFSET(s, d) \
314 #define NO_BLEND BLEND_OFFSET(GEN7_BLENDFACTOR_ONE, GEN7_BLENDFACTOR_ZERO)
315 #define CLEAR BLEND_OFFSET(GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_ZERO)
379 src, dst, (int)BLEND_OFFSET(src, dst)));
380 return BLEND_OFFSET(src, dst);
841 gen7_emit_cc(struct sna *sna, uint32_t blend_offset)
845 if (render->blend == blend_offset)
848 DBG(("%s: blend = %x\n", __FUNCTION__, blend_offset));
854 assert (is_aligned(render->cc_blend + blend_offset, 64));
856 OUT_BATCH((render->cc_blend + blend_offset) | 1)
[all...] |
| gen3_render.c | 2128 uint32_t blend_offset = sna->kgem.nbatch; local
2137 sna->kgem.batch + blend_offset + 1,
2139 sna->kgem.nbatch = blend_offset;
2141 state->last_blend = blend_offset;
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| gen7_render.c | 273 #define BLEND_OFFSET(s, d) \
277 #define NO_BLEND BLEND_OFFSET(GEN7_BLENDFACTOR_ONE, GEN7_BLENDFACTOR_ZERO)
278 #define CLEAR BLEND_OFFSET(GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_ZERO)
342 src, dst, (int)BLEND_OFFSET(src, dst)));
343 return BLEND_OFFSET(src, dst);
804 gen7_emit_cc(struct sna *sna, uint32_t blend_offset)
808 if (render->blend == blend_offset)
811 DBG(("%s: blend = %x\n", __FUNCTION__, blend_offset));
817 assert (is_aligned(render->cc_blend + blend_offset, 64));
819 OUT_BATCH((render->cc_blend + blend_offset) | 1)
[all...] |
| gen3_render.c | 2104 uint32_t blend_offset = sna->kgem.nbatch; local
2113 sna->kgem.batch + blend_offset + 1,
2115 sna->kgem.nbatch = blend_offset;
2117 state->last_blend = blend_offset;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| iris_state.c | 5770 uint32_t blend_offset; local
5774 4 * (header_dwords + rt_dwords), 64, &blend_offset);
5786 ptr.BlendStatePointer = blend_offset;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/ |
| iris_state.c | 4611 uint32_t blend_offset; local
4615 4 * (header_dwords + rt_dwords), 64, &blend_offset);
4627 ptr.BlendStatePointer = blend_offset;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/ |
| crocus_state.c | 6132 uint32_t blend_offset; local
6135 4 * rt_dwords, 64, &blend_offset);
6191 ptr.PointertoBLEND_STATE = blend_offset;
6196 ptr.BlendStatePointer = blend_offset;
|
