Searched refs:bpe (Results 1 - 25 of 72) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c35 tileb = 8 * 8 * surf->bpe;
68 unsigned bpe)
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe;
80 unsigned bpe)
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
92 unsigned flags, unsigned bpe,
108 surf_drm->bpe = bpe;
158 bpe * surf_drm->nsamples);
185 surf_ws->bpe
66 surf_level_winsys_to_drm(struct radeon_surface_level * level_drm,const struct legacy_surf_level * level_ws,unsigned bpe) argument
78 surf_level_drm_to_winsys(struct legacy_surf_level * level_ws,const struct radeon_surface_level * level_drm,unsigned bpe) argument
90 surf_winsys_to_drm(struct radeon_surface * surf_drm,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,const struct radeon_surf * surf_ws) argument
283 radeon_winsys_surface_init(struct radeon_winsys * rws,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,struct radeon_surf * surf_ws) argument
314 unsigned fmask_flags, bpe; local in function:radeon_winsys_surface_init
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c65 unsigned flags, unsigned bpe,
78 surf->bpe = bpe;
63 amdgpu_surface_init(struct radeon_winsys * rws,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,struct radeon_surf * surf) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c65 unsigned flags, unsigned bpe,
78 surf->bpe = bpe;
63 amdgpu_surface_init(struct radeon_winsys * rws,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,struct radeon_surf * surf) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c35 tileb = 8 * 8 * surf->bpe;
68 unsigned bpe)
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe;
80 unsigned bpe)
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
92 unsigned flags, unsigned bpe,
108 surf_drm->bpe = bpe;
158 bpe * surf_drm->nsamples);
185 surf_ws->bpe
66 surf_level_winsys_to_drm(struct radeon_surface_level * level_drm,const struct legacy_surf_level * level_ws,unsigned bpe) argument
78 surf_level_drm_to_winsys(struct legacy_surf_level * level_ws,const struct radeon_surface_level * level_drm,unsigned bpe) argument
90 surf_winsys_to_drm(struct radeon_surface * surf_drm,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,const struct radeon_surf * surf_ws) argument
349 radeon_winsys_surface_init(struct radeon_winsys * rws,const struct pipe_resource * tex,unsigned flags,unsigned bpe,enum radeon_surf_mode mode,struct radeon_surf * surf_ws) argument
380 unsigned fmask_flags, bpe; local in function:radeon_winsys_surface_init
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/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_surface.c169 unsigned bpe, unsigned level,
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
351 surf_minify(surf, surf->level+i, surf->bpe,
167 surf_minify(struct radeon_surface * surf,struct radeon_surface_level * surflevel,unsigned bpe,unsigned level,uint32_t xalign,uint32_t yalign,uint32_t zalign,uint64_t offset) argument
570 eg_surf_minify(struct radeon_surface * surf,struct radeon_surface_level * surflevel,unsigned bpe,unsigned level,unsigned slice_pt,unsigned mtilew,unsigned mtileh,unsigned mtileb,uint64_t offset) argument
611 eg_surface_init_1d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,uint64_t offset,unsigned start_level) argument
652 eg_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1421 si_surf_minify(struct radeon_surface * surf,struct radeon_surface_level * surflevel,unsigned bpe,unsigned level,uint32_t xalign,uint32_t yalign,uint32_t zalign,uint32_t slice_align,uint64_t offset) argument
1469 si_surf_minify_2d(struct radeon_surface * surf,struct radeon_surface_level * surflevel,unsigned bpe,unsigned level,unsigned slice_pt,uint32_t xalign,uint32_t yalign,uint32_t zalign,unsigned mtileb,uint64_t offset) argument
1550 si_surface_init_1d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,uint64_t offset,unsigned start_level) argument
1617 si_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned num_pipes,unsigned num_banks,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1857 cik_get_2d_params(struct radeon_surface_manager * surf_man,unsigned bpe,unsigned nsamples,bool is_color,unsigned tile_mode,uint32_t * num_pipes,uint32_t * tile_split_ptr,uint32_t * num_banks,uint32_t * macro_tile_aspect,uint32_t * bank_w,uint32_t * bank_h) argument
2215 cik_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned tile_split,unsigned num_pipes,unsigned num_banks,uint64_t offset,unsigned start_level) argument
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H A Dradeon_surface.h119 uint32_t bpe; member in struct:radeon_surface
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Ddrmmode_display.h115 extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
116 extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_shaderlib_nir.c87 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
95 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
134 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe,
H A Dsi_sdma_copy_image.c34 if (dst->surface.bpe != src->surface.bpe)
61 return util_logbase2(tex->surface.bpe) |
115 unsigned bpp = sdst->surface.bpe;
228 unsigned bpp = sdst->surface.bpe;
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.c465 tileb = 8 * 8 * surf->bpe;
479 unsigned bpe = surf->bpe; local in function:get_display_flag
490 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
492 (bpe == 2 && num_channels >= 3) ||
494 (bpe == 1 && num_channels == 1))
623 * blk_w, blk_h, bpe, flags.
681 switch (surf->bpe) {
693 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe *
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H A Dac_surface.h175 unsigned bpe:5; member in struct:radeon_surf
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_texture.c57 if (rdst->surface.bpe != rsrc->surface.bpe)
180 rtex->surface.bpe;
193 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
210 unsigned i, bpe, flags = 0; local in function:r600_init_surface
217 bpe = 4; /* stencil is allocated separately on evergreen */
219 bpe = util_format_get_blocksize(ptex->format);
220 assert(util_is_power_of_two_or_zero(bpe));
249 flags, bpe, array_mode, surface);
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
606 unsigned flags, bpe; local in function:r600_texture_get_fmask_info
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_texture.c58 if (rdst->surface.bpe != rsrc->surface.bpe)
181 rtex->surface.bpe;
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
211 unsigned i, bpe, flags = 0; local in function:r600_init_surface
218 bpe = 4; /* stencil is allocated separately on evergreen */
220 bpe = util_format_get_blocksize(ptex->format);
221 assert(util_is_power_of_two_or_zero(bpe));
248 flags, bpe, array_mode, surface);
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
601 unsigned flags, bpe; local in function:r600_texture_get_fmask_info
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/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Ddrmmode_display.h248 extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
249 extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_vce_50.c128 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
129 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
H A Dradeon_vce.c226 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
466 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
469 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
H A Dradeon_vce_40_2_2.c88 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
89 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
318 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
319 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
H A Dradeon_uvd_enc_1_1.c848 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
850 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
854 enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
856 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
980 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
982 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
986 enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
988 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
H A Dradeon_vce_52.c187 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
188 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
191 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch
192 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch
263 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
264 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
271 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch
272 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c796 tileb = 8 * 8 * surf->bpe;
809 unsigned bpe = surf->bpe; local in function:get_display_flag
826 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
828 (bpe == 2 && num_channels >= 3) ||
830 (bpe == 1 && num_channels == 1))
956 * blk_w, blk_h, bpe, flags.
1017 switch (surf->bpe) {
1028 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe *
3137 ac_nir_dcc_addr_from_coord(nir_builder * b,const struct radeon_info * info,unsigned bpe,struct gfx9_meta_equation * equation,nir_ssa_def * dcc_pitch,nir_ssa_def * dcc_height,nir_ssa_def * dcc_slice_size,nir_ssa_def * x,nir_ssa_def * y,nir_ssa_def * z,nir_ssa_def * sample,nir_ssa_def * pipe_xor) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_vce_50.c125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
H A Dradeon_vce.c223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
453 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
457 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
H A Dradeon_vce_40_2_2.c85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_dma.c232 bpp = sdst->surface.bpe;
233 dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x * sdst->surface.bpe;
234 src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x * ssrc->surface.bpe;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_dcc_retile.c64 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe,
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,

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