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  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
radeon_drm_surface.c 35 tileb = 8 * 8 * surf->bpe;
68 unsigned bpe)
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe;
80 unsigned bpe)
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
92 unsigned flags, unsigned bpe,
108 surf_drm->bpe = bpe;
158 bpe * surf_drm->nsamples);
185 surf_ws->bpe = surf_drm->bpe
314 unsigned fmask_flags, bpe; local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/amdgpu/drm/
amdgpu_surface.c 65 unsigned flags, unsigned bpe,
78 surf->bpe = bpe;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
amdgpu_surface.c 65 unsigned flags, unsigned bpe,
78 surf->bpe = bpe;
  /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
radeon_drm_surface.c 35 tileb = 8 * 8 * surf->bpe;
68 unsigned bpe)
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe;
80 unsigned bpe)
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
92 unsigned flags, unsigned bpe,
108 surf_drm->bpe = bpe;
158 bpe * surf_drm->nsamples);
185 surf_ws->bpe = surf_drm->bpe
380 unsigned fmask_flags, bpe; local
    [all...]
  /xsrc/external/mit/libdrm/dist/radeon/
radeon_surface.c 169 unsigned bpe, unsigned level,
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset)
    [all...]
radeon_surface.h 119 uint32_t bpe; member in struct:radeon_surface
  /xsrc/external/mit/xf86-video-ati/dist/src/
drmmode_display.h 115 extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
116 extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_shaderlib_nir.c 87 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
95 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
134 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe,
si_sdma_copy_image.c 34 if (dst->surface.bpe != src->surface.bpe)
61 return util_logbase2(tex->surface.bpe) |
115 unsigned bpp = sdst->surface.bpe;
228 unsigned bpp = sdst->surface.bpe;
  /xsrc/external/mit/MesaLib.old/dist/src/amd/common/
ac_surface.c 465 tileb = 8 * 8 * surf->bpe;
479 unsigned bpe = surf->bpe; local
490 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
492 (bpe == 2 && num_channels >= 3) ||
494 (bpe == 1 && num_channels == 1))
623 * blk_w, blk_h, bpe, flags.
681 switch (surf->bpe) {
693 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8
    [all...]
ac_surface.h 175 unsigned bpe:5; member in struct:radeon_surf
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
r600_texture.c 58 if (rdst->surface.bpe != rsrc->surface.bpe)
181 rtex->surface.bpe;
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
211 unsigned i, bpe, flags = 0; local
218 bpe = 4; /* stencil is allocated separately on evergreen */
220 bpe = util_format_get_blocksize(ptex->format);
221 assert(util_is_power_of_two_or_zero(bpe));
248 flags, bpe, array_mode, surface);
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
601 unsigned flags, bpe; local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
r600_texture.c 57 if (rdst->surface.bpe != rsrc->surface.bpe)
180 rtex->surface.bpe;
193 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
210 unsigned i, bpe, flags = 0; local
217 bpe = 4; /* stencil is allocated separately on evergreen */
219 bpe = util_format_get_blocksize(ptex->format);
220 assert(util_is_power_of_two_or_zero(bpe));
249 flags, bpe, array_mode, surface);
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
606 unsigned flags, bpe; local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/amd/common/
ac_surface.c 796 tileb = 8 * 8 * surf->bpe;
809 unsigned bpe = surf->bpe; local
826 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
828 (bpe == 2 && num_channels >= 3) ||
830 (bpe == 1 && num_channels == 1))
956 * blk_w, blk_h, bpe, flags.
1017 switch (surf->bpe) {
1028 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8
    [all...]
ac_surface.h 311 uint8_t bpe : 5; member in struct:radeon_surf
480 unsigned bpe, struct gfx9_meta_equation *equation,
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
radeon_vce_50.c 125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
radeon_vce.c 223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
453 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
457 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
radeon_vce_40_2_2.c 85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
radeon_uvd_enc_1_1.c 760 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
762 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
764 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
765 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
879 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
881 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
883 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
885 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
radeon_vce_50.c 128 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
129 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
radeon_vce.c 226 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
466 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
469 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
radeon_vce_40_2_2.c 88 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
89 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
318 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
319 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
  /xsrc/external/mit/xf86-video-ati-kms/dist/src/
drmmode_display.h 248 extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
249 extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_dma.c 232 bpp = sdst->surface.bpe;
233 dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x * sdst->surface.bpe;
234 src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x * ssrc->surface.bpe;
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_meta_dcc_retile.c 64 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe,
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
104 * - BPE
108 * BPE is always 4 at the moment and the rest is derived from the tilemode.

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