Searched refs:cb_dcc_base (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3051 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base; local in function:si_emit_framebuffer_state
3079 cb_dcc_base = 0;
3114 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3118 cb_dcc_base |= dcc_tile_swizzle;
3152 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3159 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
3197 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3198 radeon_emit(S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3218 if (cb_dcc_base)
3219 cb_dcc_base
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3039 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base; local in function:si_emit_framebuffer_state
3075 cb_dcc_base = 0;
3097 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3099 cb_dcc_base |= tex->surface.tile_swizzle;
3136 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3137 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3157 if (cb_dcc_base)
3158 cb_dcc_base += level_info->dcc_offset >> 8;
3199 radeon_emit(cs, cb_dcc_base);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_private.h1804 uint64_t cb_dcc_base; member in struct:radv_color_buffer_info
H A Dradv_cmd_buffer.c1070 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1071 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1090 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
H A Dradv_device.c4309 cb->cb_dcc_base = va >> 8;
4310 cb->cb_dcc_base |= surf->tile_swizzle;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c1766 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1775 cb->cb_dcc_base >> 32);
1795 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1796 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1816 cb->cb_dcc_base);
H A Dradv_private.h1247 uint64_t cb_dcc_base; member in struct:radv_color_buffer_info
H A Dradv_device.c6685 cb->cb_dcc_base = va >> 8;
6686 cb->cb_dcc_base |= dcc_tile_swizzle;

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