Searched refs:db_depth_control (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_state.c405 unsigned db_depth_control, alpha_test_control, alpha_ref; local in function:r600_create_dsa_state
420 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
426 db_depth_control |= S_028800_STENCIL_ENABLE(1);
427 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
428 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
429 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
430 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
433 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
434 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
435 db_depth_control |
[all...]
H A Devergreen_state.c417 unsigned db_depth_control, alpha_test_control, alpha_ref; local in function:evergreen_create_dsa_state
432 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
438 db_depth_control |= S_028800_STENCIL_ENABLE(1);
439 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
440 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
441 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
442 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
445 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
446 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
447 db_depth_control |
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_state.c410 unsigned db_depth_control, alpha_test_control, alpha_ref; local in function:r600_create_dsa_state
425 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
431 db_depth_control |= S_028800_STENCIL_ENABLE(1);
432 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
433 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
434 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
435 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
438 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
439 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
440 db_depth_control |
[all...]
H A Devergreen_state.c422 unsigned db_depth_control, alpha_test_control, alpha_ref; local in function:evergreen_create_dsa_state
437 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
443 db_depth_control |= S_028800_STENCIL_ENABLE(1);
444 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
445 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
446 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
447 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
450 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
451 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
452 db_depth_control |
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_pipeline.c2717 uint32_t db_depth_control = 0, db_stencil_control = 0; local in function:radv_pipeline_generate_depth_stencil_state
2728 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2738 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2739 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2744 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2778 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c1168 unsigned db_depth_control; local in function:si_create_dsa_state
1180 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1187 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1188 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1194 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1195 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1212 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c1261 unsigned db_depth_control; local in function:si_create_dsa_state
1273 db_depth_control =
1279 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1280 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1289 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1290 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1310 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c1798 uint32_t db_depth_control = 0; local in function:radv_pipeline_init_depth_stencil_state
1808 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
1815 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1816 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp);
1817 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp);
1821 pipeline->graphics.db_depth_control = db_depth_control;
H A Dradv_cmd_buffer.c1348 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=
1349 pipeline->graphics.db_depth_control)
1576 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control; local in function:radv_emit_depth_control
1579 db_depth_control &= C_028800_Z_ENABLE &
1588 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0) |
1597 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
H A Dradv_private.h1811 unsigned db_depth_control; member in struct:radv_pipeline::__anon4674665a290a::__anon4674665a2a08

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