| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| radeon_dma.c | 207 make_empty_list(&rmesa->dma.free);
208 make_empty_list(&rmesa->dma.wait);
209 make_empty_list(&rmesa->dma.reserved);
210 rmesa->dma.minimum_size = MAX_DMA_BUF_SZ;
218 if (size > rmesa->dma.minimum_size)
219 rmesa->dma.minimum_size = (size + 15) & (~15);
222 __func__, size, rmesa->dma.minimum_size);
224 if (is_empty_list(&rmesa->dma.free)
225 || last_elem(&rmesa->dma.free)->bo->size < size) {
231 0, rmesa->dma.minimum_size, 4
425 struct radeon_dma *dma = &rmesa->dma; local
[all...] |
| radeon_ioctl.h | 93 if ( rmesa->radeon.dma.flush ) \
94 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \
|
| radeon_queryobj.c | 113 if (radeon->dma.flush)
114 radeon->dma.flush(&radeon->glCtx);
153 if (radeon->dma.flush)
154 radeon->dma.flush(&radeon->glCtx);
|
| radeon_cmdbuf.h | 103 if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
|
| radeon_tcl.c | 60 * dma buffers. Use strip/fan hardware primitives where possible.
150 if (rmesa->radeon.dma.flush)
151 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
503 if ( rmesa->radeon.dma.flush )
504 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
506 rmesa->radeon.dma.flush = NULL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| radeon_dma.c | 206 make_empty_list(&rmesa->dma.free);
207 make_empty_list(&rmesa->dma.wait);
208 make_empty_list(&rmesa->dma.reserved);
209 rmesa->dma.minimum_size = MAX_DMA_BUF_SZ;
217 if (size > rmesa->dma.minimum_size)
218 rmesa->dma.minimum_size = (size + 15) & (~15);
221 __func__, size, rmesa->dma.minimum_size);
223 if (is_empty_list(&rmesa->dma.free)
224 || last_elem(&rmesa->dma.free)->bo->size < size) {
230 0, rmesa->dma.minimum_size, 4
424 struct radeon_dma *dma = &rmesa->dma; local
[all...] |
| radeon_ioctl.h | 93 if ( rmesa->radeon.dma.flush ) \
94 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \
|
| radeon_queryobj.c | 112 if (radeon->dma.flush)
113 radeon->dma.flush(&radeon->glCtx);
152 if (radeon->dma.flush)
153 radeon->dma.flush(&radeon->glCtx);
|
| radeon_cmdbuf.h | 103 if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
|
| radeon_tcl.c | 61 * dma buffers. Use strip/fan hardware primitives where possible.
151 if (rmesa->radeon.dma.flush)
152 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
504 if ( rmesa->radeon.dma.flush )
505 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
507 rmesa->radeon.dma.flush = NULL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/ |
| svga_resource_buffer_upload.c | 58 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
60 * It will flush and retry in case the first attempt to create a DMA buffer
110 * Allocate DMA'ble or Updatable storage for the buffer.
122 assert(sbuf->handle || !sbuf->dma.pending);
135 assert(!sbuf->dma.pending);
209 sbuf->dma.flags.discard = TRUE;
453 assert(sbuf->dma.updates == NULL);
455 if (sbuf->dma.flags.discard) {
517 sbuf->dma.updates = whole_update_cmd;
525 memcpy(whole_update_cmd, sbuf->dma.updates, sizeof(*whole_update_cmd))
[all...] |
| svga_resource_buffer.c | 83 * function) into a single DMA command, for better efficiency in command
85 * the end result is exactly the same as if one DMA was used for every mapped
141 if (sbuf->dma.pending) {
165 * Flush any pending primitives, finish writing any pending DMA
167 * the next DMA operation.
172 if (sbuf->dma.pending) {
188 sbuf->dma.flags.discard = TRUE;
195 * not synchronize on the next DMA command.
198 sbuf->dma.flags.unsynchronized = TRUE;
203 * pending DMA command, and ensure the next DMA will be done in order
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/ |
| svga_resource_buffer_upload.c | 58 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
60 * It will flush and retry in case the first attempt to create a DMA buffer
112 * Allocate DMA'ble or Updatable storage for the buffer.
124 assert(sbuf->handle || !sbuf->dma.pending);
137 assert(!sbuf->dma.pending);
224 sbuf->dma.flags.discard = TRUE;
465 assert(sbuf->dma.updates == NULL);
467 if (sbuf->dma.flags.discard) {
529 sbuf->dma.updates = whole_update_cmd;
537 memcpy(whole_update_cmd, sbuf->dma.updates, sizeof(*whole_update_cmd))
[all...] |
| svga_resource_buffer.c | 88 * function) into a single DMA command, for better efficiency in command
90 * the end result is exactly the same as if one DMA was used for every mapped
146 if (sbuf->dma.pending) {
166 * Flush any pending primitives, finish writing any pending DMA
168 * the next DMA operation.
173 if (sbuf->dma.pending) {
189 sbuf->dma.flags.discard = TRUE;
196 * not synchronize on the next DMA command.
199 sbuf->dma.flags.unsynchronized = TRUE;
204 * pending DMA command, and ensure the next DMA will be done in order
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| r600_pipe_common.c | 241 struct radeon_cmdbuf *cs = rctx->dma.cs;
254 uint64_t vram = ctx->dma.cs->used_vram;
255 uint64_t gtt = ctx->dma.cs->used_gart;
266 /* Flush the GFX IB if DMA depends on it. */
283 * This heuristic makes sure that DMA requests are executed
285 * It improves texture upload performance by keeping the DMA
289 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
290 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
291 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt))
[all...] |
| evergreen_hw_context.c | 38 struct radeon_cmdbuf *cs = rctx->b.dma.cs;
67 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ, 0);
68 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
143 /* CP DMA is executed in ME, but index buffers are read by PFP.
144 * This ensures that ME (CP DMA) is idle before PFP starts fetching
145 * indices. If we wanted to execute CP DMA in PFP, this packet
|
| r600_buffer_common.c | 40 if (radeon_emitted(ctx->dma.cs, 0) &&
41 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
76 if (radeon_emitted(ctx->dma.cs, 0) &&
77 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
80 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
83 ctx->dma.flush(ctx, 0, NULL);
95 if (ctx->dma.cs)
96 ctx->ws->cs_sync_flush(ctx->dma.cs);
339 (dword_aligned && (rctx->dma.cs ||
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| r600_pipe_common.c | 218 struct radeon_cmdbuf *cs = &rctx->dma.cs;
231 uint64_t vram = (uint64_t)ctx->dma.cs.used_vram_kb * 1024;
232 uint64_t gtt = (uint64_t)ctx->dma.cs.used_gart_kb * 1024;
243 /* Flush the GFX IB if DMA depends on it. */
260 * This heuristic makes sure that DMA requests are executed
262 * It improves texture upload performance by keeping the DMA
266 if (!ctx->ws->cs_check_space(&ctx->dma.cs, num_dw, false) ||
267 ctx->dma.cs.used_vram_kb + ctx->dma.cs.used_gart_kb > 64 * 1024 ||
268 !radeon_cs_memory_below_limit(ctx->screen, &ctx->dma.cs, vram, gtt))
[all...] |
| evergreen_hw_context.c | 38 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
67 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ, 0);
68 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
143 /* CP DMA is executed in ME, but index buffers are read by PFP.
144 * This ensures that ME (CP DMA) is idle before PFP starts fetching
145 * indices. If we wanted to execute CP DMA in PFP, this packet
|
| r600_buffer_common.c | 41 if (radeon_emitted(&ctx->dma.cs, 0) &&
42 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, buf, usage)) {
77 if (radeon_emitted(&ctx->dma.cs, 0) &&
78 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs,
81 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
84 ctx->dma.flush(ctx, 0, NULL);
96 if (ctx->dma.cs.priv)
97 ctx->ws->cs_sync_flush(&ctx->dma.cs);
337 (dword_aligned && (rctx->dma.cs.priv ||
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| r200_ioctl.h | 75 if ( rmesa->radeon.dma.flush ) \
76 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \
|
| r200_tcl.c | 143 if (rmesa->radeon.dma.flush == r200FlushElts &&
154 if (rmesa->radeon.dma.flush)
155 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
547 if ( rmesa->radeon.dma.flush )
548 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
550 rmesa->radeon.dma.flush = NULL;
614 if ( rmesa->radeon.dma.flush )
615 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
627 if ( rmesa->radeon.dma.flush )
628 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx )
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| r200_ioctl.h | 75 if ( rmesa->radeon.dma.flush ) \
76 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \
|
| r200_tcl.c | 143 if (rmesa->radeon.dma.flush == r200FlushElts &&
154 if (rmesa->radeon.dma.flush)
155 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
547 if ( rmesa->radeon.dma.flush )
548 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
550 rmesa->radeon.dma.flush = NULL;
614 if ( rmesa->radeon.dma.flush )
615 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );
627 if ( rmesa->radeon.dma.flush )
628 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx )
[all...] |
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_accel.c | 385 * random bogus DMA in case we inadvertently trigger the engine
676 drmDMAReq dma; local
689 dma.context = DRIGetContext(pScrn->pScreen);
692 dma.context = 0x00000001;
695 dma.send_count = 0;
696 dma.send_list = NULL;
697 dma.send_sizes = NULL;
698 dma.flags = 0;
699 dma.request_count = 1;
700 dma.request_size = RADEON_BUFFER_SIZE
[all...] |
