Searched refs:flush_bits (Results 1 - 25 of 30) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c817 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
963 uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits,
970 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
972 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE) {
977 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
985 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
990 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
995 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1002 } else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA) {
1006 if (flush_bits
962 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
1138 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
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H A Dradv_meta_clear.c1011 uint32_t clear_word, flush_bits; local in function:radv_fast_clear_depth
1021 cmd_buffer->state.flush_bits |= bits & ~*pre_flush;
1022 *pre_flush |= cmd_buffer->state.flush_bits;
1033 flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word);
1042 cmd_buffer->state.flush_bits |= flush_bits;
1047 *post_flush |= flush_bits;
1464 uint32_t flush_bits = 0; local in function:radv_clear_dcc
1502 flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
1505 return flush_bits;
1626 uint32_t flush_bits = 0; local in function:radv_clear_htile
1856 uint32_t clear_color[2], flush_bits = 0; local in function:radv_fast_clear_color
2412 enum radv_cmd_flush_bits flush_bits = 0; local in function:radv_cmd_clear_image
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H A Dradv_meta_fmask_expand.c110 cmd_buffer->state.flush_bits |= radv_dst_access_flush(
162 cmd_buffer->state.flush_bits |=
167 cmd_buffer->state.flush_bits |= radv_init_fmask(cmd_buffer, image, subresourceRange);
H A Dradv_query.c881 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;
884 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
1348 uint32_t flush_bits = 0; local in function:radv_CmdResetQueryPool
1354 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
1356 flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, firstQuery * pool->stride,
1360 flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,
1364 if (flush_bits) {
1367 cmd_buffer->state.flush_bits |= flush_bits;
1447 cmd_buffer->state.flush_bits
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H A Dradv_cmd_buffer.c2409 cmd_buffer->state.flush_bits |=
2434 cmd_buffer->state.flush_bits |=
3736 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
3744 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3752 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
3799 enum radv_cmd_flush_bits flush_bits = 0; local in function:radv_src_access_flush
3817 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3819 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3827 flush_bits |= RADV_CMD_FLAG_WB_L2;
3833 flush_bits |
3877 enum radv_cmd_flush_bits flush_bits = 0; local in function:radv_dst_access_flush
7417 uint32_t flush_bits = 0; local in function:radv_init_dcc
7463 uint32_t flush_bits = 0; local in function:radv_init_color_image_metadata
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H A Dradv_meta_buffer.c313 uint32_t flush_bits = 0; local in function:radv_fill_buffer
319 cmd_buffer->state.flush_bits |=
324 flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
333 return flush_bits;
H A Dradv_meta_copy_vrs_htile.c235 cmd_buffer->state.flush_bits |=
303 cmd_buffer->state.flush_bits |=
H A Dradv_meta_dcc_retile.c195 state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, image) |
287 state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
H A Dradv_meta_fast_clear.c612 cmd_buffer->state.flush_bits |=
618 cmd_buffer->state.flush_bits |=
724 cmd_buffer->state.flush_bits |=
809 cmd_buffer->state.flush_bits |=
908 cmd_buffer->state.flush_bits |=
913 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff);
H A Dradv_meta_resolve.c324 cmd_buffer->state.flush_bits |=
347 cmd_buffer->state.flush_bits |=
506 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff);
709 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_img, &range, 0xffffffff);
805 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
807 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
H A Dradv_meta_resolve_cs.c764 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE;
774 cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dest_image, &range, 0xffffffff);
836 cmd_buffer->state.flush_bits |=
857 cmd_buffer->state.flush_bits |=
922 cmd_buffer->state.flush_bits |=
940 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value);
H A Dradv_meta_copy.c558 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE;
570 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value);
H A Dradv_meta_decompress.c624 cmd_buffer->state.flush_bits |=
712 cmd_buffer->state.flush_bits |=
719 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_pipe_control.c190 const uint32_t flush_bits[NUM_IRIS_DOMAINS] = { local in function:iris_emit_buffer_barrier_for
227 bits |= flush_bits[i];
246 bits |= flush_bits[i];
267 bits |= flush_bits[i];
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c652 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
779 enum radv_cmd_flush_bits flush_bits,
783 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
786 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
788 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
792 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
815 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
821 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
826 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
831 if (flush_bits
774 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,uint64_t gfx9_eop_bug_va) argument
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H A Dradv_cmd_buffer.c2283 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2294 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2302 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2312 enum radv_cmd_flush_bits flush_bits = 0; local in function:radv_src_access_flush
2327 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2330 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2332 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2335 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2337 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2340 flush_bits |
2362 enum radv_cmd_flush_bits flush_bits = 0; local in function:radv_dst_access_flush
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H A Dradv_meta_clear.c1022 uint32_t clear_word, flush_bits; local in function:radv_fast_clear_depth
1029 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1031 *pre_flush |= cmd_buffer->state.flush_bits;
1036 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1042 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1050 *post_flush |= flush_bits;
1493 uint32_t clear_color[2], flush_bits = 0; local in function:radv_fast_clear_color
1497 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1499 *pre_flush |= cmd_buffer->state.flush_bits;
1518 flush_bits
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H A Dradv_meta_fast_clear.c686 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
753 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
822 state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
825 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, 0xffffffff);
827 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
H A Dradv_meta_buffer.c410 uint32_t flush_bits = 0; local in function:radv_fill_buffer
417 flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
427 return flush_bits;
H A Dradv_query.c1015 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
1019 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
1432 uint32_t flush_bits = 0; local in function:radv_CmdResetQueryPool
1434 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1439 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1444 if (flush_bits) {
1447 cmd_buffer->state.flush_bits |= flush_bits;
1543 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1544 cmd_buffer->state.flush_bits |
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H A Dradv_meta_resolve.c304 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
324 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
H A Dradv_meta_resolve_fs.c404 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
444 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
H A Dradv_meta_fmask_expand.c187 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
H A Dradv_meta_resolve_cs.c562 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c115 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
116 cmd_buffer->state.cache.flush_bits = 0;
125 if (!cmd_buffer->state.renderpass_cache.flush_bits &&
128 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits);
129 cmd_buffer->state.renderpass_cache.flush_bits = 0;
142 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
171 cmd_buffer->state.cache.flush_bits = 0;
1570 cache->flush_bits = 0;
2108 cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
2134 cmd_buffer->state.cache.flush_bits |
2649 enum tu_cmd_flush_bits flush_bits = 0; local in function:tu_flush_for_access
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