Searched refs:gen9 (Results 1 - 25 of 37) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen9_render.c271 .name = "Skylake (gen9)",
276 .name = "Skylake (gen9)",
281 .name = "Broxton (gen9)",
286 .name = "Kabylake (gen9)",
291 .name = "Geminilake (gen9)",
296 .name = "Coffeelake (gen9)",
582 OUT_BATCH(sna->render_state.gen9.info->urb.max_vs_entries << URB_ENTRY_NUMBER_SHIFT |
617 sna->render_state.gen9.general_bo,
623 sna->render_state.gen9.general_bo,
627 num_pages = sna->render_state.gen9
[all...]
H A Dsna_render.h155 } gen9; member in union:sna_composite_op::__anon7bfac980050a
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.6.3.rst61 - i965/gen9: Use custom MOCS entries set up by the kernel.
H A D10.6.1.rst48 - i965/gen9: Implement Push Constant Buffer workaround
H A D17.2.5.rst125 - intel/compiler/gen9: Pixel shader header only workaround
H A D20.1.10.rst51 - intel/gen9: Enable MSC RAW Hazard Avoidance
H A D10.5.9.rst61 - i965/gen9: Implement Push Constant Buffer workaround
H A D13.0.3.rst88 - genxml/gen9: Change the default of
H A D18.1.8.rst149 - i965/gen7_urb: Re-emit PUSH_CONSTANT_ALLOC on some gen9
H A D18.1.9.rst98 - i965: Workaround the gen9 hw astc5x5 sampler bug
H A D20.2.1.rst53 - intel/gen9: Enable MSC RAW Hazard Avoidance
H A D20.3.1.rst37 - \[gen9][iris][regression][bisected\] flaky piglit tests
H A D17.3.4.rst45 Disable regular fast-clears (CCS_D) on gen9+"
165 - Re-enable regular fast-clears (CCS_D) on gen9+
H A D17.2.7.rst151 - i965: Disable regular fast-clears (CCS_D) on gen9+
H A D18.2.1.rst120 - i965: Workaround the gen9 hw astc5x5 sampler bug
H A D20.2.5.rst41 - [gen9][iris][regression][bisected] flaky piglit tests
H A D11.1.0.rst43 - GL_ARB_shader_stencil_export on i965 (gen9+)
64 - 16x multisampling on i965 (gen9+)
H A D13.0.0.rst29 - OpenGL ES 3.2 on i965/gen9+ (Skylake and later)
54 - GL_ANDROID_extension_pack_es31a on i965/gen9+
H A D17.0.0.rst28 - GL_ARB_post_depth_coverage on i965/gen9+
30 - GL_INTEL_conservative_rasterization on i965/gen9+
H A D18.0.0.rst215 Disable regular fast-clears (CCS_D) on gen9+"
/xsrc/external/mit/MesaLib.old/dist/src/intel/
H A DAndroid.genxml.mk95 $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML := $(LOCAL_PATH)/genxml/gen9.xml
96 $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml $(LOCAL_PATH)/genxml/gen_pack_header.py
H A DAndroid.vulkan.mk182 # libanv for gen9
H A DMakefile.sources143 genxml/gen9.xml \
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A DAndroid.mk64 # libiris for gen9
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Dgen8_cmd_buffer.c421 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
422 * across different state packets for gen8 and gen9. We handle that by
521 pipeline->gen9.wm_depth_stencil);

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