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    Searched refs:gfx7 (Results 1 - 5 of 5) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/amd/compiler/
aco_opcodes.py 322 # GFX6, GFX7, GFX8, GFX9, GFX10, name
379 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
380 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
385 # GFX6, GFX7, GFX8, GFX9, GFX10, name
415 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
416 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
421 # GFX6, GFX7, GFX8, GFX9, GFX10, name
493 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
494 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
499 # GFX6, GFX7, GFX8, GFX9, GFX10, nam
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  /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
gfx7_cmd_buffer.c 168 cmd_buffer->state.gfx.gfx7.index_buffer = buffer;
169 cmd_buffer->state.gfx.gfx7.index_type = vk_to_intel_index_type(indexType);
170 cmd_buffer->state.gfx.gfx7.index_offset = offset;
262 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
334 pipeline->gfx7.depth_stencil_state,
343 if (cmd_buffer->state.gfx.gfx7.index_buffer &&
347 struct anv_buffer *buffer = cmd_buffer->state.gfx.gfx7.index_buffer;
348 uint32_t offset = cmd_buffer->state.gfx.gfx7.index_offset;
361 ib.IndexFormat = cmd_buffer->state.gfx.gfx7.index_type;
405 anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm)
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genX_pipeline.c 594 * hardware what line mode to use like we had on gfx7, we now have an
769 /* Gfx7 requires that we provide the depth format in 3DSTATE_SF so that it
792 GENX(3DSTATE_SF_pack)(NULL, &pipeline->gfx7.sf, &sf);
803 * 3DSTATE_MULTISAMPLE on Gfx7/7.5 by passing NULL locations.
806 /* If the sample locations are dynamic, 3DSTATE_MULTISAMPLE on Gfx7/7.5
1094 # define depth_stencil_dw pipeline->gfx7.depth_stencil_state
1235 pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
1506 GENX(3DSTATE_CLIP_pack)(NULL, pipeline->gfx7.clip, &clip);
1527 # define streamout_state_dw pipeline->gfx7.streamout_state
1567 pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride
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anv_private.h 874 * gfx7 platforms, we are limited by GTT size unless we want to implement
2939 } gfx7; member in struct:anv_cmd_graphics_state
3600 } gfx7; member in struct:anv_graphics_pipeline
genX_cmd_buffer.c 187 /* On gfx7, we have upper bounds instead. According to the docs,
450 /* We don't do any HiZ or depth fast-clears on gfx7 yet */
692 /* On gfx7, we have to store a texturable version of the stencil buffer in
1097 /* On gfx7, the combination of commands used here(MI_LOAD_REGISTER_MEM
3511 pipeline->gfx7.clip);
3521 # define streamout_state_dw pipeline->gfx7.streamout_state
3670 /* We don't have SOBufferEnable in 3DSTATE_SO_BUFFER on Gfx7 so
3674 sob.SurfacePitch = pipeline->gfx7.xfb_bo_pitch[idx];
5961 * VERTEX_BUFFER_STATE on gfx7, we need to dirty vertex buffers at the top
6618 /* On gfx7, we have to store a texturable version of the stencil buffer i
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