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    Searched refs:gfx8 (Results 1 - 5 of 5) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/amd/compiler/
aco_opcodes.py 322 # GFX6, GFX7, GFX8, GFX9, GFX10, name
379 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
385 # GFX6, GFX7, GFX8, GFX9, GFX10, name
415 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
421 # GFX6, GFX7, GFX8, GFX9, GFX10, name
493 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
499 # GFX6, GFX7, GFX8, GFX9, GFX10, name
521 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
527 # GFX6, GFX7, GFX8, GFX9, GFX10, name
568 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
gfx8_cmd_buffer.c 51 * gfx8 struct adds the min/max viewport fields. */
453 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx8.sf);
506 pipeline->gfx8.raster);
509 /* Stencil reference values moved from COLOR_CALC_STATE in gfx8 to
511 * across different state packets for gfx8 and gfx9. We handle that by
578 pipeline->gfx8.wm_depth_stencil);
712 anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.wm);
722 anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.ps_blend);
765 pipeline->gfx8.blend_state, num_dwords, 64);
genX_pipeline.c 592 /* Unfortunately, configuring our line rasterization hardware on gfx8
788 GENX(3DSTATE_SF_pack)(NULL, pipeline->gfx8.sf, &sf);
789 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gfx8.raster, &raster);
807 * will be emitted dynamically, so skip it here. On Gfx8+
822 /* On Gfx8+ 3DSTATE_MULTISAMPLE does not hold anything we need to modify
1096 # define depth_stencil_dw pipeline->gfx8.wm_depth_stencil
1235 pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
1387 GENX(3DSTATE_PS_BLEND_pack)(NULL, pipeline->gfx8.ps_blend, &blend);
1529 # define streamout_state_dw pipeline->gfx8.streamout_state
2208 uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm
    [all...]
anv_private.h 2832 * With the exception of gfx8, the bottom 12 bits of this address' offset
2872 * On Gfx8-9, the VF cache only considers the bottom 32 bits of memory
3011 * Whether or not the gfx8 PMA fix is enabled. We ensure that, at the top
3610 } gfx8; member in struct:anv_graphics_pipeline
4160 /* For Gfx8-11, there are some restrictions around sampling from HiZ.
4485 * a nice float/integer union like Gfx8+, Haswell specifies the integer border
genX_cmd_buffer.c 484 * portion of a HiZ buffer. Testing has revealed that Gfx8 only supports
485 * returning 0.0f. Gens prior to gfx8 do not support this feature at all.
924 /* On gfx8, we don't have a concept of default clear colors because we
1767 * There is also a workaround on gfx8 which requires us to invalidate the
3209 /* This field exists since Gfx8. However, the Broadwell PRM says:
3523 # define streamout_state_dw pipeline->gfx8.streamout_state

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