Searched refs:lane (Results 1 - 25 of 45) sorted by relevance

12

/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/valhall/
H A Dvalhall.py101 def __init__(self, index, size, is_float = False, swizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
109 self.lane = lane
125 if lane:
126 self.offset['lane'] = self.lane
127 self.bits['lane'] = 2 if size in (8, 32) else 1
151 self.lane = False
203 lane = el.get('lane', Non
[all...]
H A Dasm.py259 elif src.lane and mod in enums[f'lane_{src.size}_bit'].bare_values:
263 encoded |= (val << src.offset['lane'])
277 die_if(not src.lane, "Instruction doesn't take a lane")
281 encoded |= (val << src.lane)
/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/
H A Dbi_lower_divergent_indirects.c31 * if (lane == 0)
33 * else if (lane == 1)
36 * else if (lane == MAX_LANE)
89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); local in function:bi_lower_divergent_indirects_impl
101 nir_push_if(b, nir_ieq_imm(b, lane, i));
H A Dcompiler.h39 * for widen = none, H00 for widen = h0, B1111 for widen = b1. For lane, also
226 bi_byte(bi_index idx, unsigned lane) argument
229 assert(lane < 4);
230 idx.swizzle = BI_SWIZZLE_B0000 + lane;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dfetch_jit.cpp373 // gather SIMD full pixels per lane then shift/mask to move each component to their
397 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:FetchJit::CreateGatherOddFormats
400 Value* index = VEXTRACT(pOffsets, C(lane));
401 Value* mask = VEXTRACT(pMask, C(lane));
419 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt8Ty, 0));
427 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
437 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
1121 for (int64_t lane local in function:GetSimdValidIndicesGfx
1195 for (int64_t lane = 0; lane < mVWidth; lane++) local in function:FetchJit::GetSimdValidIndicesHelper
1413 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle8bpcGatherd16
1789 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather16
2035 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather
[all...]
H A Dbuilder_mem.cpp234 /// @param pVecPassthru - SIMD wide vector of values to load when lane is inactive
447 // after pshufb: group components together in each 128bit lane
453 // after PERMD: move and pack xy components into each 128bit lane
479 // if x or z, extract 128bits from lane 0, else for y or w, extract from lane 1
480 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle16bpcGather4
485 vGatherOutput[swizzleIndex] = VEXTRACT(selectedPermute, C(lane));
502 // shuffle enabled components into lower word of each 32bit lane, 0 extending to 32 bits
547 // after pshufb: group components together in each 128bit lane
553 // after PERMD: move and pack xy and zw components in low 64 bits of each 128bit lane
580 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle8bpcGather4
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dfetch_jit.cpp368 // gather SIMD full pixels per lane then shift/mask to move each component to their
391 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:FetchJit::CreateGatherOddFormats
394 Value* index = VEXTRACT(pOffsets, C(lane));
395 Value* mask = VEXTRACT(pMask, C(lane));
412 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt8Ty, 0));
420 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
430 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
1115 for (int64_t lane local in function:FetchJit::GetSimdValidIndicesHelper
1333 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle8bpcGatherd16
1703 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather16
1949 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather
[all...]
H A Dbuilder_mem.cpp234 /// @param pVecPassthru - SIMD wide vector of values to load when lane is inactive
442 // after pshufb: group components together in each 128bit lane
448 // after PERMD: move and pack xy components into each 128bit lane
474 // if x or z, extract 128bits from lane 0, else for y or w, extract from lane 1
475 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle16bpcGather4
480 vGatherOutput[swizzleIndex] = VEXTRACT(selectedPermute, C(lane));
497 // shuffle enabled components into lower word of each 32bit lane, 0 extending to 32 bits
542 // after pshufb: group components together in each 128bit lane
548 // after PERMD: move and pack xy and zw components in low 64 bits of each 128bit lane
575 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle8bpcGather4
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp122 Value *lane = bld.mkImm(l); local in function:nv50_ir::GM107LoweringPass::handleManualTXD
124 // Make sure lane 0 has the appropriate array/depth compare values
127 bld.mkOp3(OP_SHFL, TYPE_F32, arr, i->getSrc(0), lane, quad);
129 bld.mkOp3(OP_SHFL, TYPE_F32, shadow, i->getSrc(array + dim + indirect), lane, quad);
132 // mov coordinates from lane l to all lanes
134 bld.mkOp3(OP_SHFL, TYPE_F32, crd[c], i->getSrc(c + array), lane, quad);
137 // add dPdx from lane l to lanes dx
139 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdx[c].get(), lane, quad);
145 // add dPdy from lane l to lanes dy
147 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdy[c].get(), lane, qua
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp141 Value *lane = bld.mkImm(l); local in function:nv50_ir::GM107LoweringPass::handleManualTXD
143 // Make sure lane 0 has the appropriate array/depth compare values
146 bld.mkOp3(OP_SHFL, TYPE_F32, arr, i->getSrc(0), lane, quad);
148 bld.mkOp3(OP_SHFL, TYPE_F32, shadow, i->getSrc(array + dim + indirect), lane, quad);
151 // mov coordinates from lane l to all lanes
153 bld.mkOp3(OP_SHFL, TYPE_F32, crd[c], i->getSrc(c + array), lane, quad);
156 // add dPdx from lane l to lanes dx
158 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdx[c].get(), lane, quad);
164 // add dPdy from lane l to lanes dy
166 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdy[c].get(), lane, qua
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_shader.cpp416 Value *pTmpPtr = ALLOCA(mFP32Ty, C(4)); // used for dummy write for lane masking
438 for (uint32_t lane = 0; lane < mVWidth; ++lane) { local in function:BuilderSWR::swr_gs_llvm_emit_vertex
439 Value *pLaneOffset = VEXTRACT(pOutputOffset, C(lane));
440 Value *pStream = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pStreams, lane});
444 Value *pLaneMask = VEXTRACT(vMask1, C(lane));
457 vData = VEXTRACT(vData, C(lane));
506 Value *pTmpPtr = ALLOCA(mInt8Ty, C(4)); // used for dummy read/write for lane masking
508 for (uint32_t lane local in function:BuilderSWR::swr_gs_llvm_end_primitive
535 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:BuilderSWR::swr_gs_llvm_epilogue
660 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:BuilderSWR::CompileGS
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/
H A Dswr_shader.cpp766 Value *pTmpPtr = ALLOCA(mFP32Ty, C(4)); // used for dummy write for lane masking
791 for (uint32_t lane = 0; lane < mVWidth; ++lane) { local in function:BuilderSWR::swr_gs_llvm_emit_vertex
792 Value *pLaneOffset = VEXTRACT(pOutputOffset, C(lane));
793 Value *pStream = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pStreams, lane});
797 Value *pLaneMask = VEXTRACT(vMask1, C(lane));
810 vData = VEXTRACT(vData, C(lane));
842 for (uint32_t lane = 0; lane < mVWidt local in function:BuilderSWR::swr_gs_llvm_emit_vertex
910 for (uint32_t lane = 0; lane < mVWidth; ++lane) { local in function:BuilderSWR::swr_gs_llvm_end_primitive
936 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:BuilderSWR::swr_gs_llvm_epilogue
1092 for (uint32_t lane = 0; lane < mVWidth; lane++) { local in function:BuilderSWR::swr_tcs_llvm_fetch_output
1213 for (uint32_t lane = 0; lane < mVWidth; lane++) { local in function:BuilderSWR::swr_tcs_llvm_store_output
1619 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:BuilderSWR::CompileGS
[all...]
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Datombios_output.c585 5400, // 1 lane, 1.62 Ghz
586 9000, // 1 lane, 2.70 Ghz
587 10800, // 2 lane, 1.62 Ghz
588 18000, // 2 lane, 2.70 Ghz
589 21600, // 4 lane, 1.62 Ghz
590 36000, // 4 lane, 2.70 Ghz
2414 static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) argument
2416 int i = DP_LANE0_1_STATUS + (lane >> 1);
2417 int s = (lane & 1) * 4;
2424 int lane; local in function:dp_clock_recovery_ok
2446 int lane; local in function:dp_channel_eq_ok
2483 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane) argument
2497 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane) argument
2561 int lane; local in function:dp_get_adjust_train
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/
H A Dpa_avx.cpp157 INLINE simd4scalar swizzleLaneN(const simdvector& v, int lane) argument
159 switch (lane)
311 INLINE simd4scalar swizzleLaneN(const simd16vector& v, int lane) argument
313 switch (lane)
505 for (uint32_t lane = 0; lane < KNOB_SIMD_WIDTH; ++lane) local in function:PaPatchListTerm
508 uint32_t input_cp = (lane + lane_offset) * TotalControlPoints + cp;
515 uint32_t input_cp = lane * TotalControlPoints + cp;
521 vec[lane]
564 for (uint32_t lane = 0; lane < KNOB_SIMD16_WIDTH; ++lane) local in function:PaPatchListTerm_simd16
1820 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local in function:PaLineLoop1
1872 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local in function:PaLineLoop1_simd16
[all...]
H A Dclip.h591 SIMD256::set_epi32(0 * sizeof(SIMDVERTEX_T<SIMD_T>), // unused lane
601 // @todo dynamic mask based on actual # of verts generated per lane
606 // transpose clipper output so that each lane's vertices are in SIMD order
626 // tranpose clipper output so that each lane's vertices are in SIMD order
854 // step to the lane
884 DWORD lane; local in function:Clipper::ScatterComponent
885 while (_BitScanForward(&lane, mask))
887 mask &= ~(1 << lane);
888 const uint8_t* pBuf = reinterpret_cast<const uint8_t*>(pBuffer) + pOffsets[lane];
889 *(float*)pBuf = pSrc[lane];
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_llvm_build.h623 ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane);
626 ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef value, LLVMValueRef lane);
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.7.rst107 - aux/draw: fix llvm tcs lane vec generation
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_llvm_build.h502 LLVMValueRef lane);
504 LLVMValueRef ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane);
507 LLVMValueRef lane);
H A Dac_llvm_build.c3376 LLVMValueRef lane, bool with_opt_barrier)
3385 if (lane)
3386 lane = LLVMBuildZExt(ctx->builder, lane, ctx->i32, "");
3389 ac_build_intrinsic(ctx, lane == NULL ? "llvm.amdgcn.readfirstlane" : "llvm.amdgcn.readlane",
3390 ctx->i32, (LLVMValueRef[]){src, lane}, lane == NULL ? 1 : 2,
3397 LLVMValueRef lane, bool with_opt_barrier)
3414 ret_comp = _ac_build_readlane(ctx, src, lane, with_opt_barrier);
3420 ret = _ac_build_readlane(ctx, src, lane, with_opt_barrie
3375 _ac_build_readlane(struct ac_llvm_context * ctx,LLVMValueRef src,LLVMValueRef lane,bool with_opt_barrier) argument
3396 ac_build_readlane_common(struct ac_llvm_context * ctx,LLVMValueRef src,LLVMValueRef lane,bool with_opt_barrier) argument
3439 ac_build_readlane_no_opt_barrier(struct ac_llvm_context * ctx,LLVMValueRef src,LLVMValueRef lane) argument
3445 ac_build_readlane(struct ac_llvm_context * ctx,LLVMValueRef src,LLVMValueRef lane) argument
3450 ac_build_writelane(struct ac_llvm_context * ctx,LLVMValueRef src,LLVMValueRef value,LLVMValueRef lane) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_512_emu.inl236 template <int ImmT> // for each 128-bit lane:
534 Integer const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (int32)
540 permute_ps(Float const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (float)
H A Dsimdlib_128_avx.inl377 permute_epi32(Integer a, Integer swiz) // return a[swiz[i]] for each 32-bit lane i (float)
383 permute_ps(Float a, Integer swiz) // return a[swiz[i]] for each 32-bit lane i (float)
H A Dsimdlib_256_avx2.inl185 permute_ps(Float const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (float)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_512_emu.inl236 template <int ImmT> // for each 128-bit lane:
534 Integer const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (int32)
540 permute_ps(Float const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (float)
H A Dsimdlib_128_avx.inl377 permute_epi32(Integer a, Integer swiz) // return a[swiz[i]] for each 32-bit lane i (float)
383 permute_ps(Float a, Integer swiz) // return a[swiz[i]] for each 32-bit lane i (float)
H A Dsimdlib_256_avx2.inl193 permute_ps(Float const& a, Integer const& swiz) // return a[swiz[i]] for each 32-bit lane i (float)

Completed in 44 milliseconds

12