| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/valhall/ |
| valhall.py | 101 def __init__(self, index, size, is_float = False, swizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
109 self.lane = lane
125 if lane:
126 self.offset['lane'] = self.lane
127 self.bits['lane'] = 2 if size in (8, 32) else 1
151 self.lane = False
203 lane = el.get('lane', None
[all...] |
| asm.py | 259 elif src.lane and mod in enums[f'lane_{src.size}_bit'].bare_values:
263 encoded |= (val << src.offset['lane'])
277 die_if(not src.lane, "Instruction doesn't take a lane")
281 encoded |= (val << src.lane)
|
| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/ |
| bi_lower_divergent_indirects.c | 31 * if (lane == 0)
33 * else if (lane == 1)
36 * else if (lane == MAX_LANE)
89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); local
101 nir_push_if(b, nir_ieq_imm(b, lane, i));
|
| bi_printer.c.py | 52 "zero", "lane-id", "wrap-id", "core-id", "fb-extent",
147 % if mod[0:-1] not in ["lane", "lanes", "replicate", "swz", "widen", "swap", "abs", "neg", "sign", "not"]:
|
| compiler.h | 39 * for widen = none, H00 for widen = h0, B1111 for widen = b1. For lane, also
226 bi_byte(bi_index idx, unsigned lane)
229 assert(lane < 4);
230 idx.swizzle = BI_SWIZZLE_B0000 + lane;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/ |
| fetch_jit.cpp | 373 // gather SIMD full pixels per lane then shift/mask to move each component to their
397 for (uint32_t lane = 0; lane < mVWidth; ++lane)
400 Value* index = VEXTRACT(pOffsets, C(lane));
401 Value* mask = VEXTRACT(pMask, C(lane));
419 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt8Ty, 0));
427 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
437 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
1121 for (int64_t lane = 0; lane < vWidth; lane++
1413 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
1789 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
2035 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
[all...] |
| builder_mem.cpp | 234 /// @param pVecPassthru - SIMD wide vector of values to load when lane is inactive
447 // after pshufb: group components together in each 128bit lane
453 // after PERMD: move and pack xy components into each 128bit lane
479 // if x or z, extract 128bits from lane 0, else for y or w, extract from lane 1
480 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
485 vGatherOutput[swizzleIndex] = VEXTRACT(selectedPermute, C(lane));
502 // shuffle enabled components into lower word of each 32bit lane, 0 extending to 32 bits
547 // after pshufb: group components together in each 128bit lane
553 // after PERMD: move and pack xy and zw components in low 64 bits of each 128bit lane
580 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_lowering_gm107.cpp | 141 Value *lane = bld.mkImm(l); local
143 // Make sure lane 0 has the appropriate array/depth compare values
146 bld.mkOp3(OP_SHFL, TYPE_F32, arr, i->getSrc(0), lane, quad);
148 bld.mkOp3(OP_SHFL, TYPE_F32, shadow, i->getSrc(array + dim + indirect), lane, quad);
151 // mov coordinates from lane l to all lanes
153 bld.mkOp3(OP_SHFL, TYPE_F32, crd[c], i->getSrc(c + array), lane, quad);
156 // add dPdx from lane l to lanes dx
158 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdx[c].get(), lane, quad);
164 // add dPdy from lane l to lanes dy
166 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdy[c].get(), lane, quad)
[all...] |
| nv50_ir_emit_nv50.cpp | 123 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
841 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp)
843 code[0] = 0xc0000000 | (lane << 16);
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_lowering_gm107.cpp | 122 Value *lane = bld.mkImm(l); local
124 // Make sure lane 0 has the appropriate array/depth compare values
127 bld.mkOp3(OP_SHFL, TYPE_F32, arr, i->getSrc(0), lane, quad);
129 bld.mkOp3(OP_SHFL, TYPE_F32, shadow, i->getSrc(array + dim + indirect), lane, quad);
132 // mov coordinates from lane l to all lanes
134 bld.mkOp3(OP_SHFL, TYPE_F32, crd[c], i->getSrc(c + array), lane, quad);
137 // add dPdx from lane l to lanes dx
139 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdx[c].get(), lane, quad);
145 // add dPdy from lane l to lanes dy
147 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdy[c].get(), lane, quad)
[all...] |
| nv50_ir_emit_nv50.cpp | 125 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
834 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp)
836 code[0] = 0xc0000000 | (lane << 16);
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/ |
| fetch_jit.cpp | 368 // gather SIMD full pixels per lane then shift/mask to move each component to their
391 for (uint32_t lane = 0; lane < mVWidth; ++lane)
394 Value* index = VEXTRACT(pOffsets, C(lane));
395 Value* mask = VEXTRACT(pMask, C(lane));
412 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt8Ty, 0));
420 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
430 Value* pDst = BITCAST(GEP(pDstMem, C(lane)), PointerType::get(mInt16Ty, 0));
1115 for (int64_t lane = 0; lane < mVWidth; lane++
1333 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
1703 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
1949 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
[all...] |
| builder_mem.cpp | 234 /// @param pVecPassthru - SIMD wide vector of values to load when lane is inactive
442 // after pshufb: group components together in each 128bit lane
448 // after PERMD: move and pack xy components into each 128bit lane
474 // if x or z, extract 128bits from lane 0, else for y or w, extract from lane 1
475 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
480 vGatherOutput[swizzleIndex] = VEXTRACT(selectedPermute, C(lane));
497 // shuffle enabled components into lower word of each 32bit lane, 0 extending to 32 bits
542 // after pshufb: group components together in each 128bit lane
548 // after PERMD: move and pack xy and zw components in low 64 bits of each 128bit lane
575 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/ |
| swr_shader.cpp | 416 Value *pTmpPtr = ALLOCA(mFP32Ty, C(4)); // used for dummy write for lane masking
438 for (uint32_t lane = 0; lane < mVWidth; ++lane) {
439 Value *pLaneOffset = VEXTRACT(pOutputOffset, C(lane));
440 Value *pStream = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pStreams, lane});
444 Value *pLaneMask = VEXTRACT(vMask1, C(lane));
457 vData = VEXTRACT(vData, C(lane));
506 Value *pTmpPtr = ALLOCA(mInt8Ty, C(4)); // used for dummy read/write for lane masking
508 for (uint32_t lane = 0; lane < mVWidth; ++lane)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/ |
| swr_shader.cpp | 766 Value *pTmpPtr = ALLOCA(mFP32Ty, C(4)); // used for dummy write for lane masking
791 for (uint32_t lane = 0; lane < mVWidth; ++lane) {
792 Value *pLaneOffset = VEXTRACT(pOutputOffset, C(lane));
793 Value *pStream = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pStreams, lane});
797 Value *pLaneMask = VEXTRACT(vMask1, C(lane));
810 vData = VEXTRACT(vData, C(lane));
842 for (uint32_t lane = 0; lane < mVWidth; ++lane)
[all...] |
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| atombios_output.c | 585 5400, // 1 lane, 1.62 Ghz
586 9000, // 1 lane, 2.70 Ghz
587 10800, // 2 lane, 1.62 Ghz
588 18000, // 2 lane, 2.70 Ghz
589 21600, // 4 lane, 1.62 Ghz
590 36000, // 4 lane, 2.70 Ghz
2414 static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane)
2416 int i = DP_LANE0_1_STATUS + (lane >> 1);
2417 int s = (lane & 1) * 4;
2424 int lane; local
2446 int lane; local
2561 int lane; local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/ |
| pa_avx.cpp | 157 INLINE simd4scalar swizzleLaneN(const simdvector& v, int lane)
159 switch (lane)
311 INLINE simd4scalar swizzleLaneN(const simd16vector& v, int lane)
313 switch (lane)
505 for (uint32_t lane = 0; lane < KNOB_SIMD_WIDTH; ++lane)
508 uint32_t input_cp = (lane + lane_offset) * TotalControlPoints + cp;
515 uint32_t input_cp = lane * TotalControlPoints + cp;
521 vec[lane] = pInputVec[input_lane]
1820 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local
1872 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local
[all...] |
| clip.h | 591 SIMD256::set_epi32(0 * sizeof(SIMDVERTEX_T<SIMD_T>), // unused lane
601 // @todo dynamic mask based on actual # of verts generated per lane
606 // transpose clipper output so that each lane's vertices are in SIMD order
626 // tranpose clipper output so that each lane's vertices are in SIMD order
854 // step to the lane
884 DWORD lane; local
885 while (_BitScanForward(&lane, mask))
887 mask &= ~(1 << lane);
888 const uint8_t* pBuf = reinterpret_cast<const uint8_t*>(pBuffer) + pOffsets[lane];
889 *(float*)pBuf = pSrc[lane];
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| ac_llvm_build.h | 623 ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane);
626 ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef value, LLVMValueRef lane);
|
| ac_llvm_build.c | 3398 _ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane)
3402 lane == NULL ? "llvm.amdgcn.readfirstlane" : "llvm.amdgcn.readlane",
3404 src, lane },
3405 lane == NULL ? 1 : 2,
3414 * @param lane - id of the lane or NULL for the first active lane
3415 * @return value of the lane
3418 ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane)
3426 ret = _ac_build_readlane(ctx, src, lane);
[all...] |
| ac_nir_to_llvm.c | 3444 unsigned lane = nir_src_as_uint(instr->src[1]); local
3446 lane, lane, lane, lane);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/llvm/ |
| ac_llvm_build.h | 502 LLVMValueRef lane);
504 LLVMValueRef ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane);
507 LLVMValueRef lane);
|
| ac_llvm_build.c | 3376 LLVMValueRef lane, bool with_opt_barrier)
3385 if (lane)
3386 lane = LLVMBuildZExt(ctx->builder, lane, ctx->i32, "");
3389 ac_build_intrinsic(ctx, lane == NULL ? "llvm.amdgcn.readfirstlane" : "llvm.amdgcn.readlane",
3390 ctx->i32, (LLVMValueRef[]){src, lane}, lane == NULL ? 1 : 2,
3397 LLVMValueRef lane, bool with_opt_barrier)
3414 ret_comp = _ac_build_readlane(ctx, src, lane, with_opt_barrier);
3420 ret = _ac_build_readlane(ctx, src, lane, with_opt_barrier)
[all...] |
| ac_nir_to_llvm.c | 4070 unsigned lane = nir_src_as_uint(instr->src[1]); local
4071 result = ac_build_quad_swizzle(&ctx->ac, get_src(ctx, instr->src[0]), lane, lane, lane, lane);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_instruction_selection.cpp | 1036 /* Turn the result into a per-lane bool */
7767 /* Copy the source and write the reduction operation identity to the first lane. */
7768 Temp lane = bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm));
7778 bld.writelane(bld.def(v1), bld.copy(bld.hint_m0(s1), Operand::c32(identity_lo)), lane, lo);
7780 bld.writelane(bld.def(v1), bld.copy(bld.hint_m0(s1), Operand::c32(identity_hi)), lane, hi);
7784 bld.writelane(dst, bld.copy(bld.hint_m0(s1), Operand::c32(identity)), lane,
8470 /* Quad broadcast lane. */
8471 unsigned lane = 0;
8483 lane = nir_src_as_const_value(instr->src[1])->u32;
8484 dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane)
[all...] |
