Searched refs:mip (Results 1 - 25 of 45) sorted by relevance

12

/xsrc/external/mit/mesa-demos/dist/src/rbug/
H A Dtex_dump.c39 int mip)
43 unsigned width = info->width[mip];
44 unsigned height = info->height[mip];
52 (unsigned long long)tex, util_format_name(info->format), mip);
36 dump(rbug_texture_t tex,struct rbug_proto_texture_info_reply * info,struct rbug_proto_texture_read_reply * read,int mip) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_resource.c154 struct etna_resource_level *mip = &rsc->levels[level]; local in function:setup_miptree
156 mip->width = width;
157 mip->height = height;
158 mip->padded_width = align(width * msaa_xscale, paddingX);
159 mip->padded_height = align(height * msaa_yscale, paddingY);
160 mip->stride = util_format_get_stride(prsc->format, mip->padded_width);
161 mip->offset = size;
162 mip->layer_stride = mip
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/common/tests/
H A Dmi_builder_test.cpp930 emit_cmd(GENX(MI_PREDICATE), mip) {
931 mip.LoadOperation = LOAD_LOAD;
932 mip.CombineOperation = COMBINE_SET;
933 mip.CompareOperation = COMPARE_TRUE;
940 emit_cmd(GENX(MI_PREDICATE), mip) {
941 mip.LoadOperation = LOAD_LOAD;
942 mip.CombineOperation = COMBINE_SET;
943 mip.CompareOperation = COMPARE_FALSE;
1055 emit_cmd(GENX(MI_PREDICATE), mip) {
1056 mip
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/include/
H A Dsvga3d_surfacedefs.h942 * Given a base level size and the mip level, compute the size of
943 * the mip level.
1053 uint32 mip)
1072 if (i < mip) {
1091 uint32 mip; local in function:svga3dsurface_get_serialized_size
1093 for (mip = 0; mip < num_mip_levels; mip++) {
1095 svga3dsurface_get_mip_size(base_level_size, mip);
1049 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,SVGA3dSize baseLevelSize,uint32 numMipLevels,uint32 layer,uint32 mip) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/include/
H A Dsvga3d_surfacedefs.h942 * Given a base level size and the mip level, compute the size of
943 * the mip level.
1053 uint32 mip)
1072 if (i < mip) {
1091 uint32 mip; local in function:svga3dsurface_get_serialized_size
1093 for (mip = 0; mip < num_mip_levels; mip++) {
1095 svga3dsurface_get_mip_size(base_level_size, mip);
1049 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,SVGA3dSize baseLevelSize,uint32 numMipLevels,uint32 layer,uint32 mip) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_resource.c172 struct etna_resource_level *mip = &rsc->levels[level]; local in function:setup_miptree
174 mip->width = width;
175 mip->height = height;
176 mip->depth = depth;
177 mip->padded_width = align(width * msaa_xscale, paddingX);
178 mip->padded_height = align(height * msaa_yscale, paddingY);
179 mip->stride = util_format_get_stride(prsc->format, mip->padded_width);
180 mip->offset = size;
181 mip
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/
H A Dr300_state_inlines.h262 static inline uint32_t r300_translate_tex_filters(int min, int mag, int mip, argument
293 switch (mip) {
304 fprintf(stderr, "r300: Unknown texture filter %d\n", mip);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/
H A Dr300_state_inlines.h262 static inline uint32_t r300_translate_tex_filters(int min, int mag, int mip, argument
293 switch (mip) {
304 fprintf(stderr, "r300: Unknown texture filter %d\n", mip);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv84_video.c272 struct nv50_miptree mip; local in function:nv84_create_decoder
479 surf.base.texture = &mip.base.base;
480 mip.level[0].tile_mode = 0;
481 mip.level[0].pitch = surf.width * 4;
482 mip.base.domain = NOUVEAU_BO_VRAM;
483 mip.base.bo = dec->mbring;
484 mip.base.address = dec->mbring->offset;
489 mip.level[0].pitch = surf.width * 4;
490 mip.base.bo = dec->vpring;
491 mip
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv84_video.c272 struct nv50_miptree mip; local in function:nv84_create_decoder
479 surf.base.texture = &mip.base.base;
480 mip.level[0].tile_mode = 0;
481 mip.level[0].pitch = surf.width * 4;
482 mip.base.domain = NOUVEAU_BO_VRAM;
483 mip.base.bo = dec->mbring;
484 mip.base.address = dec->mbring->offset;
489 mip.level[0].pitch = surf.width * 4;
490 mip.base.bo = dec->vpring;
491 mip
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c641 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
642 mip.LoadOperation = LOAD_LOADINV;
643 mip.CombineOperation = COMBINE_SET;
644 mip.CompareOperation = COMPARE_SRCS_EQUAL;
684 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
685 mip.LoadOperation = LOAD_LOADINV;
686 mip.CombineOperation = COMBINE_SET;
687 mip.CompareOperation = COMPARE_SRCS_EQUAL;
3138 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
3139 mip
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.cpp367 * Get meta mip info
374 UINT_32 numMipLevels, ///< [in] number of mip levels
377 ADDR2_META_MIP_INFO* pInfo, ///< [out] meta mip info
463 for (UINT_32 mip = 0; mip < numMipLevels; mip++) local in function:Addr::V2::Gfx9Lib::GetMetaMipInfo
467 GetMetaMiptailInfo(&pInfo[mip], mipCoord, numMipLevels - mip,
477 pInfo[mip].inMiptail = FALSE;
478 pInfo[mip]
4274 for (UINT_32 mip = 0; mip < numMipInTail; mip++) local in function:Addr::V2::Gfx9Lib::GetMetaMiptailInfo
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.cpp405 * Get meta mip info
412 UINT_32 numMipLevels, ///< [in] number of mip levels
415 ADDR2_META_MIP_INFO* pInfo, ///< [out] meta mip info
501 for (UINT_32 mip = 0; mip < numMipLevels; mip++) local in function:Addr::V2::Gfx9Lib::GetMetaMipInfo
505 GetMetaMiptailInfo(&pInfo[mip], mipCoord, numMipLevels - mip,
515 pInfo[mip].inMiptail = FALSE;
516 pInfo[mip]
4580 for (UINT_32 mip = 0; mip < numMipInTail; mip++) local in function:Addr::V2::Gfx9Lib::GetMetaMiptailInfo
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c889 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
890 mip.LoadOperation = LOAD_LOADINV;
891 mip.CombineOperation = COMBINE_SET;
892 mip.CompareOperation = COMPARE_SRCS_EQUAL;
932 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
933 mip.LoadOperation = LOAD_LOADINV;
934 mip.CombineOperation = COMBINE_SET;
935 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4424 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
4425 mip
[all...]
H A DgenX_query.c1302 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
1303 mip.LoadOperation = LOAD_LOAD;
1304 mip.CombineOperation = COMBINE_SET;
1305 mip.CompareOperation = COMPARE_SRCS_EQUAL;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D7.8.3.rst38 mip image.
H A D17.0.2.rst65 - radv: disable mip point pre clamping.
H A D18.2.7.rst34 - RADV/Vega: Low mip levels of large BCn textures get corrupted by
H A D20.2.5.rst56 - radv: Deal with unused attachments in mip flush
/xsrc/external/mit/mesa-demos/dist/src/trivial/
H A DMakefile.am146 tri-fbo-tex-mip \
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c4516 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4517 mip.LoadOperation = LOAD_LOAD;
4518 mip.CombineOperation = COMBINE_SET;
4519 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4526 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4527 mip.LoadOperation = LOAD_LOAD;
4528 mip.CombineOperation = COMBINE_OR;
4529 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4536 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4537 mip
[all...]
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c4445 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4446 mip.LoadOperation = LOAD_LOAD;
4447 mip.CombineOperation = COMBINE_SET;
4448 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4455 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4456 mip.LoadOperation = LOAD_LOAD;
4457 mip.CombineOperation = COMBINE_OR;
4458 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4465 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4466 mip
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/cso/
H A Dsampler.rst64 The texture mip filter modes are:
/xsrc/external/mit/MesaLib/dist/docs/gallium/cso/
H A Dsampler.rst64 The texture mip filter modes are:
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_state.c7484 * mip-mapping. However, we can fake it by offsetting to the
7508 * mip-mapping. However, we can fake it by offsetting to the
8209 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8210 mip.LoadOperation = LOAD_LOAD;
8211 mip.CombineOperation = COMBINE_SET;
8212 mip.CompareOperation = COMPARE_SRCS_EQUAL;
8219 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8220 mip.LoadOperation = LOAD_LOAD;
8221 mip.CombineOperation = COMBINE_OR;
8222 mip
[all...]

Completed in 55 milliseconds

12