| /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 73 level_drm->nblk_y = level_ws->nblk_y; 85 level_ws->nblk_y = level_drm->nblk_y; 261 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8); 345 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 73 level_drm->nblk_y = level_ws->nblk_y; 85 level_ws->nblk_y = level_drm->nblk_y; 261 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8); 337 height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); 411 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
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| /xsrc/external/mit/libdrm/dist/radeon/ |
| H A D | radeon_surface.h | 76 uint32_t nblk_y; member in struct:radeon_surface_level
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| H A D | radeon_surface.c | 177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; 181 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { 187 surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); 192 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y; 586 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; 590 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { 596 surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); 602 mtile_ps = (mtile_pr * surflevel->nblk_y) / mtile [all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_dma.c | 131 tiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1; 137 height = tiled->surface.u.legacy.level[tiled_lvl].nblk_y; 245 ssrc->surface.u.legacy.level[src_level].nblk_y != 246 sdst->surface.u.legacy.level[dst_level].nblk_y) {
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| H A D | ac_surface.h | 83 unsigned nblk_y:15; member in struct:legacy_surf_level
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| H A D | ac_surface.c | 350 surf_level->nblk_y = AddrSurfInfoOut->height; 597 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | radeon_vce.c | 231 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); 456 align(tmp_surf->u.legacy.level[0].nblk_y, 32);
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| H A D | r600_texture.c | 261 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4; 650 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; 801 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8); 871 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " 879 rtex->surface.u.legacy.level[i].nblk_y, 889 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " 897 rtex->surface.u.legacy.stencil_level[i].nblk_y,
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| H A D | r600_state.c | 834 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1048 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1071 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; 2876 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); 2895 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | radeon_vce.c | 235 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); 456 align(tmp_surf->u.legacy.level[0].nblk_y, 32);
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| H A D | r600_texture.c | 260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4; 645 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; 796 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8); 866 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " 874 rtex->surface.u.legacy.level[i].nblk_y, 884 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " 892 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y,
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| H A D | r600_state.c | 837 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1051 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1074 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; 2880 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); 2899 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_vce_50.c | 127 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| H A D | radeon_vce.c | 227 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); 467 align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
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| H A D | radeon_vce_40_2_2.c | 90 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw 317 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| H A D | radeon_uvd_enc.c | 350 align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
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| H A D | radeon_vcn_enc.c | 324 align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
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| H A D | radeon_vce_52.c | 189 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw 262 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_vce_50.c | 124 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| H A D | radeon_vce.c | 224 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); 454 align(tmp_surf->u.legacy.level[0].nblk_y, 32)
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| H A D | radeon_vce_40_2_2.c | 87 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw 314 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| H A D | radeon_uvd_enc.c | 326 align(tmp_surf->u.legacy.level[0].nblk_y, 32)
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| H A D | radeon_vce_52.c | 196 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw 269 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
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| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| H A D | ac_surface.h | 96 unsigned nblk_y : 15; member in struct:legacy_surf_level
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